US3969150A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of MOS transistor manufacture
Assignee: Fairchild Semiconductor Corp
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Filing: 1975-01-27
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Granted: 1976-07-13
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Expires: 1995-01-27
Abstract
Abstract A metal-oxide-semiconductor (MOS) transistor structure includes gate, source and drain regions. Said structure also includes a gate electrode electrically connected and contiguous to either the source region or the drain region. Typically, the gate electrode is formed of a conductive material through which impurity diffusions may pass substantially unimpeded.
Inventors
- 👤 Robert L. Luce
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 15:32
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/027; H10D64/00; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/517; H10D64/519; H10W; H10W74/00; H10W74/10; H10W74/131; H10W74/137
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
256 words
A method of manufacturing a semiconductor structure having spaced diffused regions for source and drain elements and a gate region therebetween, said gate region including an overlying electrode insulatively spaced therefrom and ohmically connected to one of said diffused regions, comprising the steps of: a. forming an insulating layer over the surface of a semiconductor substrate including the area for said structure; b. defining and etching a first opening in said insulating layer thereby exposing a first area of the surface of said substrate for a first of said diffused regions; c. forming a layer of polycrystalline silicon over said insulating layer and within said first opening; d. defining and etching said polycrystalline silicon layer over said first area thereby exposing a portion of said first area such that a portion of said polycrystalline silicon layer remains in contact with the surface of said substrate and the remainder of said polycrystalline silicon layer extends from said first area over said insulating layer adjacent to said first area; e. defining and etching a second opening in said insulating layer adjacent to said polycrystalline silicon layer and spaced from said first area thereby exposing a second area of the surface of said substrate; f. diffusing an impurity into the structure thereby rendering said polycrystalline silicon layer conductive as a gate electrode, and thereby forming said first and second diffused regions in said substrate beneath said first and second areas of the surface of said substrate, wherein said gate electrode is formed in ohmic contact with said first region.
Claim 2
Independent Claim
256 words
A method of manufacturing a semiconductor structure having spaced diffused regions for source and drain elements and a gate region therebetween, said gate region including an overlying electrode insulatively spaced therefrom and ohmically connected to one of said diffused regions, comprising the steps of: a. forming an insulating layer over the surface of a semiconductor substrate including the area for said structure; b. defining and etching a first opening in said insulating layer thereby exposing a first area of the surface of said substrate for a first of said diffused regions; c. forming a layer of polycrystalline silicon over said insulating layer and within said first opening; d. defining and etching said polycrystalline silicon layer over said first area thereby exposing a portion of said first area such that a portion of said polycrystalline silicon layer remains in contact with the surface of said substrate and the remainder of said polycrystalline silicon layer extends from said first area over said insulating layer adjacent to said first area; e. defining and etching a second opening in said insulating layer adjacent to said polycrystalline silicon layer and spaced from said first area thereby exposing a second area of the surface of said substrate; f. diffusing an impurity into the structure thereby rendering said polycrystalline silicon layer conductive as a gate electrode, and thereby forming said first and second diffused regions in said substrate beneath said first and second areas of the surface of said substrate, wherein said gate electrode is formed in ohmic contact with said first region.
Claim 3
Dependent Claim
17 words
A method as in claim 1 wherein said diffusion step is performed by means of ion implantation.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-07-13 | 1980-01-12 | 1980-07-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-07-13 | 1984-01-12 | 1984-07-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-07-13 | 1988-01-12 | 1988-07-13 | $7700.00 | Window Closed / Lapsed |