Patent US3963905A successfully refreshed from Google Patents.
US3963905A
Expired / Lapsed
US
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Periodic sequence generators using ordinary arithmetic
Assignee: AT&T Inc
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Filing: 1975-05-02
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Granted: 1976-06-15
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Expires: 1995-05-02
Abstract
Abstract Disclosed are signal generators for developing multilevel output signal sequences of a preselected period of repetition. In their general form, the generators comprise a shift register capable of storing multilevel signals, and feedback means. The feedback means multiply the output signal of prescribed shift register stages by selected integers, add the multiplied signals in nonmodulo arithmetic, and apply the added signals to the first stage of the shift register. The multiplying integers within the feedback means are selected to cause the characteristic functions of the signal generator to be a cyclotomic polynomial. For descriptive convenience, the disclosed generator is termed a "cyclotomic circuit." The disclosed cyclotomic circuits are particularly useful in a minimum memory, prescribed-period, signal generator applications. The minimum memory is achieved by separating the prescribed period into power-of-prime factors, and by associating with each factor a cyclotomic circuit. Each cyclotomic circuit develops a subsequence signal of a period equal to the power-of-prime factor, and the subsequence signals are combined in a transversal network, responsive to the cyclotomic circuits, to form the desired prescribed period sequence signal. Advantageously, the multiplying feedback integers of cyclotomic circuits of power-of-prime periods are limited to 0, 1, and -1.
Inventors
- 👤 Bhaskarpillai Gopinath
- 👤 Robert Paul Kurshan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 12:14
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/58; G06F7/582; G06F7/584; H; H03; H03B; H03B29/00; H03K; H03K3/00; H03K3/78; H03K3/84; H04; H04L; H04L9/00; H04L9/06; H04L9/065; H04L9/0656; H04L9/0662; G06F2207/00; G06F2207/58; G06F2207/581; G06F2207/583; Y; Y04; Y04S; Y04S40/00; Y04S40/20
Claims Analysis
Total Claims: 29
Claim 1
Independent Claim
62 words
A circuit comprising: a shift register; means for multiplying the output signals of selected stages of said shift register by predetermined integers to cause the characteristic function of said circuit to be a cyclotomic polynomial; means for forming a non-modulo sum signal of said integer multiplied signals; and means for applying said sum signal to the first stage of said shift register.
Claim 2
Dependent Claim
62 words
A circuit comprising: a shift register; means for multiplying the output signals of selected stages of said shift register by predetermined integers to cause the characteristic function of said circuit to be a cyclotomic polynomial; means for forming a non-modulo sum signal of said integer multiplied signals; and means for applying said sum signal to the first stage of said shift register.
Claim 3
Dependent Claim
114 words
A circuit comprising: a shift register of k stages having at least one of said k stages at a nonzero initial condition; means for forming product signals β j (x n ) j where (x n ) j is the output signal of the j th stage of said shift register at time n and β j is a predetermined multiplicative integer associated with the j th stage of said shift register, such that for a function variable λ, the function ##EQU19## is a cyclotomic polynomial; means for adding said product signals to form a signal ##EQU20## and means for applying said x n +1 signal to the first stage of said shift register.
Claim 4
Dependent Claim
114 words
A circuit comprising: a shift register of k stages having at least one of said k stages at a nonzero initial condition; means for forming product signals β j (x n ) j where (x n ) j is the output signal of the j th stage of said shift register at time n and β j is a predetermined multiplicative integer associated with the j th stage of said shift register, such that for a function variable λ, the function ##EQU19## is a cyclotomic polynomial; means for adding said product signals to form a signal ##EQU20## and means for applying said x n +1 signal to the first stage of said shift register.
Claim 5
Dependent Claim
59 words
A multilevel sequence generator comprising: an analog shift register of k stages; and feedback means interposed between selected stages of said shift register and the first stage of said shift register for developing a multilevel nonmodula negative sum of the multilevel output signals of said selected stages as an input signal to said first stage of said shift register.
Claim 6
Dependent Claim
59 words
A multilevel sequence generator comprising: an analog shift register of k stages; and feedback means interposed between selected stages of said shift register and the first stage of said shift register for developing a multilevel nonmodula negative sum of the multilevel output signals of said selected stages as an input signal to said first stage of said shift register.
Claim 7
Dependent Claim
18 words
The sequence generator of claim 3 wherein said feedback means develops said nonmodula negative sum in ordinary arithmetic.
Claim 8
Dependent Claim
26 words
The sequence generator of claim 3 wherein said feedback means comprises means for quantizing said multilevel input signal to said first stage to preselected signal levels.
Claim 9
Dependent Claim
72 words
A multilevel signal generator comprising: a shift register; means for multiplying the output signals of preselected stages of said shift register by -1 where said preselected stages are chosen to provide a characteristic function for said signal generator that is a cyclotomic polynomial; means for adding said multiplied signals in nonmodulo arithmetic; and means for applying the output signal of said means for adding to the first stage of said shift register.
Claim 10
Dependent Claim
72 words
A multilevel signal generator comprising: a shift register; means for multiplying the output signals of preselected stages of said shift register by -1 where said preselected stages are chosen to provide a characteristic function for said signal generator that is a cyclotomic polynomial; means for adding said multiplied signals in nonmodulo arithmetic; and means for applying the output signal of said means for adding to the first stage of said shift register.
Claim 11
Dependent Claim
72 words
A multilevel signal generator comprising: a shift register; first means for reversing the output signal polarity of a first set of preselected stages of said shift register; means for adding said polarity reversed signals and the output signals of a second set of preselected stages of said shift register in nonmodulo arithmetic; and means for applying the output signal of said means for adding to the first stage of said shift register.
Claim 12
Dependent Claim
72 words
A multilevel signal generator comprising: a shift register; first means for reversing the output signal polarity of a first set of preselected stages of said shift register; means for adding said polarity reversed signals and the output signals of a second set of preselected stages of said shift register in nonmodulo arithmetic; and means for applying the output signal of said means for adding to the first stage of said shift register.
Claim 13
Dependent Claim
104 words
A sequence generator, responsive to a clock signal, providing an output signal of period q v , where q is a prime number and v is a positive integer comprising: a shift register having (q v -1 )(q-1) stages, in which the signal of the (i)th stage transfers to the (i+1)th stage at the occurrence of said clock signal; means for reversing the output signal polarity of each (q v -1 )th stage of said shift register; means for adding said polarity reversed signals; and means for applying the output signal of said means for adding to the first stage of said shift register.
Claim 14
Dependent Claim
104 words
A sequence generator, responsive to a clock signal, providing an output signal of period q v , where q is a prime number and v is a positive integer comprising: a shift register having (q v -1 )(q-1) stages, in which the signal of the (i)th stage transfers to the (i+1)th stage at the occurrence of said clock signal; means for reversing the output signal polarity of each (q v -1 )th stage of said shift register; means for adding said polarity reversed signals; and means for applying the output signal of said means for adding to the first stage of said shift register.
Claim 15
Dependent Claim
109 words
A multilevel analog sequence generator, responsive to a clock signal and providing a sequence of period q v , where q is a prime number and v is a positive integer comprising: a shift register having (q v -1 )(q-1) stages where the signal of the register's (i)th stage is transferred to the register's (i+1)th stage at the occurrence of said clock signal; means for summing the output signal of each (q v -1 )th stage of said shift register; and means interposed between said means for summing and the first stage of said shift register for reversing the polarity of the output signal of said means for adding.
Claim 16
Dependent Claim
109 words
A multilevel analog sequence generator, responsive to a clock signal and providing a sequence of period q v , where q is a prime number and v is a positive integer comprising: a shift register having (q v -1 )(q-1) stages where the signal of the register's (i)th stage is transferred to the register's (i+1)th stage at the occurrence of said clock signal; means for summing the output signal of each (q v -1 )th stage of said shift register; and means interposed between said means for summing and the first stage of said shift register for reversing the polarity of the output signal of said means for adding.
Claim 17
Dependent Claim
96 words
A sequence generator responsive to a clock signal providing a sequence of period q v , where q is a prime number and v is a positive integer comprising: a shift register having (q v -1 )(q-1) stages; means for reversing the output signal polarity of stages counted in the direction of signal flow which are multiples of q v -1 to provide feedback signals; and means interposed between said means for polarity reversing and the first stage of said shift register for summing said feedback signals and applying the sum thereof to said 1st stage.
Claim 18
Dependent Claim
96 words
A sequence generator responsive to a clock signal providing a sequence of period q v , where q is a prime number and v is a positive integer comprising: a shift register having (q v -1 )(q-1) stages; means for reversing the output signal polarity of stages counted in the direction of signal flow which are multiples of q v -1 to provide feedback signals; and means interposed between said means for polarity reversing and the first stage of said shift register for summing said feedback signals and applying the sum thereof to said 1st stage.
Claim 19
Dependent Claim
119 words
A sequence generator responsive to a clock signal providing a sequence of period 2q v where q is a prime number and v is a positive integer comprising: a shift register having (q v -1 )(q-1) stages where the signal of the (i)th stage is transferred to the (i+1)th stage at the occurrence of said clock signal; means for reversing the output signal polarity of stages which are multiples of 2(Q v -1 ) to provide feedback signals; means for adding said feedback signals and the output signal of stages which are odd multiples of (q v -1 ); and means for applying the output signal of said means for adding to the first stage of said shift register.
Claim 20
Dependent Claim
119 words
A sequence generator responsive to a clock signal providing a sequence of period 2q v where q is a prime number and v is a positive integer comprising: a shift register having (q v -1 )(q-1) stages where the signal of the (i)th stage is transferred to the (i+1)th stage at the occurrence of said clock signal; means for reversing the output signal polarity of stages which are multiples of 2(Q v -1 ) to provide feedback signals; means for adding said feedback signals and the output signal of stages which are odd multiples of (q v -1 ); and means for applying the output signal of said means for adding to the first stage of said shift register.
Claim 21
Dependent Claim
81 words
A sequence generator comprising: an analog shift register; feedback means connected to chosen stages of said shift register for combining the output signals of said chosen stages to form a negative nonmodulo sum thereof and for applying the combined signal to the first stage of said shift register; and a transversal network connected to preselected stages of said analog shift register for providing an output sequence that corresponds to a combination of the output signals of said preselected shift register stages.
Claim 22
Dependent Claim
81 words
A sequence generator comprising: an analog shift register; feedback means connected to chosen stages of said shift register for combining the output signals of said chosen stages to form a negative nonmodulo sum thereof and for applying the combined signal to the first stage of said shift register; and a transversal network connected to preselected stages of said analog shift register for providing an output sequence that corresponds to a combination of the output signals of said preselected shift register stages.
Claim 23
Dependent Claim
124 words
A signal generator providing a multilevel output sequence of period p, where p is a product of powers of prime numbers, comprising: a plurality of subsequence generators, each corresponding to one of said powers of prime numbers and developing a signal subsequent of length equal to its corresponding power of prime number comprising; A. a shift register; B. means for adding the output signal of selected stages of said shift register; and C. means interposed between said means for adding and the first stage of said shift register for reversing the polarity of the output signal of said means for adding; and a transversal network responsive to selected stages of each of said subsequence generators for providing said multilevel output sequence of period p.
Claim 24
Dependent Claim
124 words
A signal generator providing a multilevel output sequence of period p, where p is a product of powers of prime numbers, comprising: a plurality of subsequence generators, each corresponding to one of said powers of prime numbers and developing a signal subsequent of length equal to its corresponding power of prime number comprising; A. a shift register; B. means for adding the output signal of selected stages of said shift register; and C. means interposed between said means for adding and the first stage of said shift register for reversing the polarity of the output signal of said means for adding; and a transversal network responsive to selected stages of each of said subsequence generators for providing said multilevel output sequence of period p.
Claim 25
Dependent Claim
15 words
The signal generator of claim 13 wherein said shift register is an analog shift register.
Claim 26
Dependent Claim
139 words
A signal generator providing a multilevel output sequence of period p, where (p,4)≠2 and where p is ##EQU21## where p i are prime numbers and α i and r are positive integers comprising: r subsequence generators, each corresponding to a p i .sup.α.sbsp.i term, comprising: A. a shift register having (p i .sup.α.sbsp.i -1 )(p i -1) stages; B. means for adding the output signals of stages which correspond to multiples of (p i .sup.α.sbsp.i -1 ); and C. means interposed between said means for adding and the first stage of said shift register for reversing the polarity of the output signal of said means for adding; and a transversal network responsive to selected stages of each of said subsequent generators for providing a multilevel output signal that corresponds to a combination of the signals of said selected stages.
Claim 27
Dependent Claim
139 words
A signal generator providing a multilevel output sequence of period p, where (p,4)≠2 and where p is ##EQU21## where p i are prime numbers and α i and r are positive integers comprising: r subsequence generators, each corresponding to a p i .sup.α.sbsp.i term, comprising: A. a shift register having (p i .sup.α.sbsp.i -1 )(p i -1) stages; B. means for adding the output signals of stages which correspond to multiples of (p i .sup.α.sbsp.i -1 ); and C. means interposed between said means for adding and the first stage of said shift register for reversing the polarity of the output signal of said means for adding; and a transversal network responsive to selected stages of each of said subsequent generators for providing a multilevel output signal that corresponds to a combination of the signals of said selected stages.
Claim 28
Dependent Claim
237 words
A signal generator providing a multilevel output sequence of period p which equals ##EQU22## where p i are prime numbers and α i and r are positive integers comprising: r-1 subsequence generators, each corresponding to a p i .sup.α.sbsp.i other than i=1 comprising: A. a shift register having (p i .sup.α.sbsp.i -1 )(p i -1) stages; B. means for adding the output signals of stages which correspond to multiples of (p i .sup.α.sbsp.i -1 ); and C. means interposed between said means for adding and the first stage of said shift register for negating the output signal of said means for adding; an r th subsequence generator comprising: A. an r th shift register having (p 1 .sup.α.sbsp.i -1 )(p 1 -1) stages; B. r th means for reversing the output polarity of stage numbers which are multiples of 2(p 1 .sup.α.sbsp.i -1 ) to provide feedback signals; C. r th means for adding said feedback signals and the output signal of stages of said r th shift register which are odd multiples of (p 1 .sup..sup.α.sbsp.i -1 ); and D. means for applying the output signal of said r th means for adding to the first stage of said r th shift register; and a transversal network responsive to selected stages of each of said subsequence generators for providing a multilevel output signal that corresponds to a linear combination of the signals of said selected stages.
Claim 29
Dependent Claim
237 words
A signal generator providing a multilevel output sequence of period p which equals ##EQU22## where p i are prime numbers and α i and r are positive integers comprising: r-1 subsequence generators, each corresponding to a p i .sup.α.sbsp.i other than i=1 comprising: A. a shift register having (p i .sup.α.sbsp.i -1 )(p i -1) stages; B. means for adding the output signals of stages which correspond to multiples of (p i .sup.α.sbsp.i -1 ); and C. means interposed between said means for adding and the first stage of said shift register for negating the output signal of said means for adding; an r th subsequence generator comprising: A. an r th shift register having (p 1 .sup.α.sbsp.i -1 )(p 1 -1) stages; B. r th means for reversing the output polarity of stage numbers which are multiples of 2(p 1 .sup.α.sbsp.i -1 ) to provide feedback signals; C. r th means for adding said feedback signals and the output signal of stages of said r th shift register which are odd multiples of (p 1 .sup..sup.α.sbsp.i -1 ); and D. means for applying the output signal of said r th means for adding to the first stage of said r th shift register; and a transversal network responsive to selected stages of each of said subsequence generators for providing a multilevel output signal that corresponds to a linear combination of the signals of said selected stages.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-06-15 | 1979-12-15 | 1980-06-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-06-15 | 1983-12-15 | 1984-06-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-06-15 | 1987-12-15 | 1988-06-15 | $7700.00 | Window Closed / Lapsed |