US3740591A
Expired / Lapsed
US
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Bucket-brigade tuned sampled data filter
Assignee: General Electric Co
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Filing: 1972-02-25
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Granted: 1973-06-19
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Expires: 1992-02-25
Abstract
Abstract A tuned filter circuit having response characteristics of a tuned LC circuit includes bucket-brigade delay lines and gain factor components connected in feedback circuit relationship around a summing amplifier, and in forward circuit relationship. The resonant frequency of the filter is primarily controlled by the frequency of a digital clock input to the bucket-brigade delay lines. The filter Q and the filter transient response are controlled by the gains established by the gain factor components.
Inventors
- 👤 D Smith
- 👤 W Butler
- 👤 C Puckette
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 14:20
CPC Classifications
H; H03; H03H; H03H15/00; H03H15/02
Claims Analysis
Total Claims: 30
Claim 1
Independent Claim
242 words
A tuned band-pass sampled data filter comprising: summing means provided with input and output terminals, a first of said summing means input terminals adapted to be supplied with an analog input signal to be processed by said filter, first bucket-brigade delay line and gain factor means serially connected in forward circuit relationship with respect to said summing means, second bucket-brigade delay line and gain factor means serially connected in feedback circuit relationship with respect to said summing means, third bucket-brigade delay line and gain factor means serially connected in negative feedback circuit relationship with respect to said summing means, and digital clock means for generating a square wave voltage waveform and complementary waveform applied to a pair of input clock terminals associated with the bucket-brigade delay lines of said bucket-brigade delay line and gain factor means for causing signals appearing at input signal terminals thereof to be sampled, held and delayed in their propagation therethrough, the processed signal appearing at a first output terminal of said summing means being a sampled data analog signal with maximum amplitude centered at the filter resonant frequency f0 1/2 pi T cos 1(K1/2 square root K2) and having a bandwidth BW 1/ pi T ln square root K2 where T is the delay time of one of the bucket-brigade delay line, and K1 and K2 are predetermined gains established by the gain factor of said second and third bucket-brigade delay line and gain factor means, respectively.
Claim 2
Dependent Claim
242 words
A tuned band-pass sampled data filter comprising: summing means provided with input and output terminals, a first of said summing means input terminals adapted to be supplied with an analog input signal to be processed by said filter, first bucket-brigade delay line and gain factor means serially connected in forward circuit relationship with respect to said summing means, second bucket-brigade delay line and gain factor means serially connected in feedback circuit relationship with respect to said summing means, third bucket-brigade delay line and gain factor means serially connected in negative feedback circuit relationship with respect to said summing means, and digital clock means for generating a square wave voltage waveform and complementary waveform applied to a pair of input clock terminals associated with the bucket-brigade delay lines of said bucket-brigade delay line and gain factor means for causing signals appearing at input signal terminals thereof to be sampled, held and delayed in their propagation therethrough, the processed signal appearing at a first output terminal of said summing means being a sampled data analog signal with maximum amplitude centered at the filter resonant frequency f0 1/2 pi T cos 1(K1/2 square root K2) and having a bandwidth BW 1/ pi T ln square root K2 where T is the delay time of one of the bucket-brigade delay line, and K1 and K2 are predetermined gains established by the gain factor of said second and third bucket-brigade delay line and gain factor means, respectively.
Claim 3
Dependent Claim
22 words
The filter set forth in claim 1 wherein: K12/4 must be less than K2 in order to obtain resonance in the filter.
Claim 4
Dependent Claim
25 words
The filter set forth in claim 1 wherein: K2 must be positive and less than unity in order to obtain stable operation of the filter.
Claim 5
Dependent Claim
29 words
The filter set forth in claim 1 wherein: K0 and K1 can be positive or negative where K0 is a predetermined gain established by said first gain factor means.
Claim 6
Dependent Claim
14 words
The filter set forth in claim 4 wherein: K0 can be of any magnitude.
Claim 7
Dependent Claim
14 words
The filter set forth in claim 1 wherein: K1 must be less than two.
Claim 8
Dependent Claim
56 words
The filter set forth in claim 1 wherein: the bandwidth of the filter is varied primarily by changing K2, and the filter resonant frequency f0 is varied primarily by changing the frequency of the digital clock means square waves which determine the bucket-brigade delay line time T, the clock frequency and gain K2 being separately adjustable.
Claim 9
Dependent Claim
20 words
The filter set forth in claim 1 wherein: said summing means includes two summing amplifiers connected in series circuit Relationship.
Claim 10
Dependent Claim
18 words
The filter set forth in claim 1 wherein: said summing means is a single electrical signal summing device.
Claim 11
Dependent Claim
23 words
The filter set forth in claim 1 wherein: said first, second and third bucket-brigade delay line means are three separate bucket-brigade delay lines.
Claim 12
Dependent Claim
27 words
The filter set forth in claim 10 wherein: said first, second and third bucket-brigade delay lines are of equal length to thereby provide equal time delays T.
Claim 13
Dependent Claim
55 words
The filter set forth in claim 1 wherein: said first bucket-brigade delay line means is a separate bucket-brigade delay line and said second and third bucket-brigade delay line means are formed as a single bucket-brigade delay line of delay time 2T and provided with a center-tap to provide a second output of delay time T.
Claim 14
Dependent Claim
77 words
The filter set forth in claim 1 wherein: said first, second and third bucket-brigade delay line means are formed as a single bucket-brigade delay line of delay time 2T and provided with a center-tap to provide a second output of delay time T, said first and second gain factor means commonly connected to an output terminal at the center-tap of the single bucket-brigade delay line, said third gain factor means connected to the 2T output terminal thereof.
Claim 15
Dependent Claim
53 words
The filter set forth in claim 1 wherein: said summing means consists of first and second serially connected summing amplifiers, an input terminal of said first summing amplifier being supplied with the analog input signal to be processed, an output terminal of said second summing amplifier providing the output sampled data analog signal.
Claim 16
Dependent Claim
96 words
The filter set forth in claim 14 wherein: said first bucket-brigade delay line and gain factor means consists of a first bucket-brigade delay line of delay time T and a first variable resistor connected in series circuit relationship, the analog input signal to be processed being supplied to the input signal terminal of said first bucket-brigade delay line, an output of said first variable resistor connected to an input terminal of a selected of said first and second summing amplifiers as determined by the polarity of a predetermined gain K0 established by said first variable resistor.
Claim 17
Dependent Claim
96 words
The filter set forth in claim 15 wherein: said second bucket-brigade delay line and gain factor means consists of a second bucket-brigade delay line of delay time T and a second variable resistor which establishes the predetermined gain K1 connected in series circuit relationship, the input signal terminal of said second bucket-brigade delay line connected to the output terminal of said second summing amplifier, an output of said second variable resistor connected to an input terminal of a selected of said first and second summing amplifiers as determined by the polarity of the predetermined gain K1.
Claim 18
Dependent Claim
86 words
The filter set forth in claim 16 wherein: said third bucket-brigade delay line and gain factor means consists of a third bucket-brigade delay line of delay time T and a third variable resistor which establishes the prdetermined gain K2 connected in series circuit relationship, the input signal terminal of said third bucket-brigade line connected to an output terminal of said second bucket-brigade line, an output of said third variable resistor connected to an input terminal of said second summing amplifier to establish the negative feedback relationship.
Claim 19
Dependent Claim
167 words
The filter set forth in claim 15 wherein: said third bucket-brigade delay line and gain factor means consists of a second bucket-brigade delay line of delay time 2T and a third variable resistor which establishes the predetermined gain K2 connected in series circuit relationship, the input signal terminal of said second bucket-brigade delay line connected to the output terminal of said second summing amplifier, an output of said third variable resistor connected to an iNput terminal of said second amplifier, and said second bucket-brigade delay line provided with a center-tap to provide a second output of delay time T, said second bucket-brigade delay line and gain factor means consists of a second variable resistor which establishes the predetermined gain K1 connected in series circuit relationship with said second bucket-brigade delay line at the center-tap thereof, an output of said second variable resistor connected to an input terminal of a selected of said first and second summing amplifiers as determined by the polarity of the predetermined gain K1.
Claim 20
Dependent Claim
112 words
The filter set forth in claim 14 wherein: said first bucket-brigade delay line and gain factor means consists of a bucket-brigade delay line of delay time 2T and provided with a center-tap to provide a second output of delay time T and a first variable resistor which establishes a predetermined gain K0 connected in series circuit relationship with said bucket-brigade delay line at the center-tap output thereof, the input signal terminal of said bucket-brigade delay line connected to the output terminal of said first summing amplifier, an output of said first variable resistor connected to an input terminal of said second summing amplifier determined by the polarity of the predetermined gain K0.
Claim 21
Dependent Claim
79 words
The filter set forth in claim 19 wherein: said second bucket-brigade delay line and gain factor means consists of said bucket-brigade delay line of delay time 2T and a second variable resistor which establishes the predetermined gain K1 connected in series circuit relationship with said bucket-brigade delay line at the center-tap output thereof, an output of said second variable resistor connected to an input terminal of said first summing amplifier determined by the polarity of the predetermined gain K1.
Claim 22
Dependent Claim
76 words
The filter set forth in claim 20 wherein: said third bucket-brigade delay line and gain factor means consists of said bucket-brigade delay line of delay time 2T and a third variable resistor which establishes the predetermined gain K2 connected in series circuit relationship with said bucket-brigade delay line at the 2T output thereof, an output of said third variable resistor connected to an input terminal of said first summing amplifier to establish the negative feedback relationship.
Claim 23
Dependent Claim
63 words
The filter set forth in claim 21 wherein: said summing amplifiers are electronic operational amplifiers provided with a plurality of summing inputs, the magnitude of the predetermined gains K0, K1 and K2 being determined by the ratio of resistances of the operational amplifier feedback resistor to that of the resistors in the summing inputs containing the first, second and third variable resistors, respectively.
Claim 24
Dependent Claim
31 words
The filter set forth in claim 22 and further comprising: means connected between the outputs of said bucket-brigade delay line and the variable resistors for providing isolation and impedance matching therebetween.
Claim 25
Dependent Claim
30 words
The filter set forth in claim 22 and further comprising: means connected at an input of said second operational amplifier for reducing any D.C. offset voltage at the output thereof.
Claim 26
Dependent Claim
39 words
The filter set forth in claim 22 and further comprising: means in communication with the input signal terminal of said bucket-brigade delay line for providing a desired bias voltage thereto for assuring the input signal thereto is of unipolarity.
Claim 27
Dependent Claim
51 words
The filter set forth in claim 19 wherein: said bucket-brigade delay line comprises an input sampling stage and a plurality of serially connected delay line stages, the input sampling stage consisting of an electronic switch and a capacitor. each delay line stage consisting of a pair of electronic switches and capacitors.
Claim 28
Dependent Claim
52 words
The filter set forth in claim 26 wherein: the electronic switches eAch consist of a field effect transistor, the capacitor in the sampling stage connected between the drain electrode of the transistor and ground, the capacitors in the delay line stages connected between the drain and gate electrodes of the respective transistors.
Claim 29
Dependent Claim
70 words
The filter set forth in claim 26 wherein: the square wave voltage waveform generated in said digital clock means is applied to the gate electrodes of the transistor in said input sampling stage and the second and alternate transistors in said delay line stages, the complementary waveform generated in said digital clock means is applied to the gate electrodes of the first and alternate transistors in said delay line stages.
Claim 30
Dependent Claim
37 words
The filter set forth in claim 26 wherein: said bucket-brigade delay line further comprises a first output source-follower stage connected at the center-tap output thereof, and a second output source-follower stage connected at the 2T output thereof.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-06-18 | 1976-12-18 | 1977-06-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-06-18 | 1980-12-18 | 1981-06-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-06-18 | 1984-12-18 | 1985-06-19 | $7700.00 | Window Closed / Lapsed |