CMOS differential amplifier circuit utilizing a CMOS current sinking transistor which tracks CMOS current sourcing transistors

Claim 2

A CMOS differential amplifier circuit including a first and second branch circuit, said amplifier circuit comprising: a first CMOS amplifier transistor a source, a drain and a gate, the source to drain circuit thereof being in said first branch circuit of said amplifier, a second CMOS amplifier transistor comprising a source, a drain, and a gate, the source to drain circuit thereof being in said second branch circuit of said amplifier parallel to said first branch circuit, a CMOS current sourcing transistor having a source, a drain, and a gate, the source to drain circuit thereof being coupled to the source to drain circuit of said first amplifier transistor in said first branch circuit, a CMOS current sinking transistor having a source, a drain, and a gate, the source to drain circuit thereof being coupled in common to the source to drain circuits of said two amplifier transistors, a source of electrical potential, said two branch circuits and the source to drain circuit of said current sinking transistor being coupled in series across said source of potential, and a CMOS control circuit for providing a first reference voltage to be applied to the gate of said current sourcing transistor and a second reference voltage to be applied to the gate of said current sinking transistor, said CMOS control circuit comprising; a first CMOS control transistor having a source, a drain, and a gate, a resistor circuit coupled in series with the source to drain circuit of said first control transistor across said source of potential, the gate of said first control transistor being coupled to the node of said resistor and said source to drain circuit of said first control transistor, the gate of said current sourcing transistor being coupled to said node whereby the voltage developed at said node is utilized as the first reference voltage to the gate of said current sourcing transistor, a second CMOS control transistor comprising a source, a drain, and a gate, the gate thereof being coupled to the node of said resistor and said source to drain circuit of said first control transistor whereby said first reference voltage is applied to the gate of said second control transistor, and a third CMOS control transistor having a source, a drain, and a gate, the source to drain circuit of said third control transistor being coupled in series with the source to drain circuit of said second control transistor across said source of potential, the gate of said third control transistor being coupled to the node of the source to drain circuits of said second control transistor and said third control transistor, the gate of said current sinking transistor being coupled to the node of said source to drain circuits of said second and third control transistors whereby the voltage developed at said node is utilized as the second reference voltage to the gate of said current sinking transistor, the ratios of the channel widths of said three control transistors, said current sourcing transistor, and said current sinking transistor being such that the value of the second reference voltage applied to the gate of the current sinking transistor produces a current limiting value therein which is about twice the current limiting value produced in said current sourcing transistor by said first reference voltage applied to the gate of said current sourcing transistor.

Claim 3

A CMOS differential amplifier circuit as claimed in claim 1 wherein the channel regions of said current sourcing transistor and said first and second control transistors are of one conductivity type and wherein the channel regions of said two amplifier transistors, said current sinking transistor, and said third control transistor are of a second conductivity type.

Claim 4

A CMOS differential amplifier circuit as claimed in claim 2 wherein said first conductivity type is P channel and said second conductivity type is N channel.

Claim 5

A CMOS differential amplifier circuit as claimed in claim 1 including a second CMOS current sourcing transistor having a source, a drain, and a gate, the source to drain circuit thereof being coupled to the source to drain circuit of said second amplifier transistor in said second branch circuit, the gate thereof being coupled to said node of said resistor and said source to drain circuit of said first control transistor, the length and width of the channel region of said second current sourcing transistor being substantially equal to the length and width, respectively, of the channel region of said first current sourcing transistor.

Claim 6

A CMOS differential amplifier circuit as claimed in claim 4 wherein the channel regions of said two current sourcing transistors and said first and second control transistors are of one conductivity type and wherein the channel regions of said two amplifier transistors, said current sinking transistor, and said third control transistor are of a second conductivity type.

Claim 7

A CMOS differential amplifier circuit as claimed in claim 5 wherein said first conductivity type is P channel and said second conductivity type is N channel.

Claim 8

A CMOS differential amplifier circuit including a first and a second branch circuit, said amplifier circuit comprising: a first CMOS amplifier transistor comprising a source, a drain and a gate, the source to drain circuit thereof being in said first branch circuit of said amplifier, a second CMOS amplifier transistor comprising a source, a drain, and a gate, the source to drain circuit thereof being in said second branch circuit of said amplifier parallel to said first branch circuit, a CMOS current sourcing transistor having a source, a drain, and a gate, the source to drain circuit thereof being coupled to the source to drain circuit of said first amplifier transistor in said first branch circuit, a CMOS current sinking transistor having a source, a drain, and a gate, the source to drain circuit thereof being coupled in common to the source to drain circuits of said two amplifier transistors, a source of electrical potential, said two branch circuits and the source to drain circuit of said current sinking transistor being coupled in series across said source of potential, and a CMOS control circuit for providing a first reference voltage to be applied to the gate of said current sourcing transistor and a second reference voltage to be applied to the gate of said current sinking transistor, said CMOS control circuit comprising: a first CMOS control transistor having a source, a drain, and a gate, a resistor circuit coupled in series with the source to drain circuit of said first control transistor across said source of potential, the gate of said first control transistor being coupled to the node of said resistor and said source to drain circuit of said first control transistor, the gate of said current sourcing transistor being coupled to the node of said resistor and said source to drain circuit of said first control transistor, the gate of said current sourcing transistor being coupled to said node whereby the voltage developed at said node is utilized as the first reference voltage to the gate of said current sourcing transistor, a second CMOS control transistor comprising a source, a drain, and a gate, the gate thereof being coupled to the node of said resistor and said source to drain circuit of said first control transistor whereby said first reference voltage is applied to the gate of said second control transistor, and a third CMOS control transistor having a source, a drain, and a gate, the source to drain circuit of said third control transistor being coupled in series with the source to drain circuit of said second control transistor across said source of potential, the gate of said third control transistor being coupled to the node of the source to drain circuits of said second control transistor and said third control transistor, the gate of said current sinking transistor being coupled to the node of said source to drain circuits of said second and third control transistors whereby the voltage developed at said node is utilized as the second reference voltage to the gate of said current sinking transistor, the CMOS transistors being so dimensioned that, with the channel lengths of said current sourcing transistor and said first and second control transistors being equal and with the channel lengths of said current sinking and said third control transistor being equal, the product of the channel widths of said current sinking transistor and said second control transistor is equal to about twice the product of the channel widths of said current sourcing transistor and said third control transistor.

Claim 9

A CMOS differential amplifier circuit including a first and a second branch circuit, said amplifier circuit comprising: a first CMOS amplifier transistor comprising a source, a drain and a gate, the source to drain circuit thereof being in said first branch circuit of said amplifier, a second CMOS amplifier transistor comprising a source, a drain, and a gate, the source to drain circuit thereof being in said second branch circuit of said amplifier parallel to said first branch circuit, a CMOS current sourcing transistor having a source, a drain, and a gate, the source to drain circuit thereof being coupled to the source to drain circuit of said first amplifier transistor in said first branch circuit, a CMOS current sinking transistor having a source, a drain, and a gate, the source to drain circuit thereof being coupled in common to the source to drain circuits of said two amplifier transistors, a source of electrical potential, said two branch circuits and the source to drain circuit of said current sinking transistor being coupled in series across said source of potential, and a CMOS control circuit for providing a first reference voltage to be applied to the gate of said current sourcing transistor and a second reference voltage to be applied to the gate of said current sinking transistor, said CMOS control circuit comprising: a first CMOS control transistor having a source, a drain, and a gate, a resistor circuit coupled in series with the source to drain circuit of said first control transistor across said source of potential, the gate of said first control transistor being coupled to the node of said resistor and said source to drain circuit of said first control transistor, the gate of said current sourcing transistor being coupled to the node of said resistor and said source to drain circuit of said first control transistor, the gate of said current sourcing transistor being coupled to said node whereby the voltage developed at said node is utilized as the first reference voltage to the gate of said current sourcing transistor, a second CMOS control transistor comprising a source, a drain, and a gate, the gate thereof being coupled to the node of said resistor and said source to drain circuit of said first control transistor whereby said first reference voltage is applied to the gate of said second control transistor, and a third CMOS control transistor having a source, a drain, and a gate, the source to drain circuit of said third control transistor being coupled in series with the source to drain circuit of said second control transistor across said source of potential, the gate of said third control transistor being coupled to the node of the source to drain circuits of said second control transistor and said third control transistor, the gate of said current sinking transistor being coupled to the node of said source to drain circuits of said second and third control transistors whereby the voltage developed at said node is utilized as the second reference voltage to the gate of said current sinking transistor, the CMOS transistors being so dimensioned that, with the channel lengths of said current sourcing transistor and said first and second control transistors being equal and with the channel lengths of said current sinking and said third control transistor being equal, the product of the channel widths of said current sinking transistor and said second control transistor is equal to about twice the product of the channel widths of said current sourcing transistor and said third control transistor.

Claim 10

A CMOS differential amplifier circuit as claimed in claim 7 wherein the channel region of said current sourcing transistor and said first and second control transistors are of one conductivity type and wherein the channel regions of said two amplifier transistors, said current sinking transistor, and said third control transistor are of a second conductivity type.

Claim 11

A CMOS differential amplifier circuit as claimed in claim 8 wherein said first conductivity type is P channel and said second conductivity type is N channel.

Claim 12

A CMOS differential amplifier circuit as claimed in claim 7 including a second CMOS current sourcing transistor having a source, a drain, and a gate, the source to drain circuit thereof being coupled to the source to drain circuit to said second amplifier transistor in said second branch circuit, the gate thereof being coupled to said node of said resistor and said source to drain circuit of said first control transistor, the length and width of the channel region of said second current sourcing transistor being substantially equal to the length and width, respectively, of the channel region of said first current sourcing transistor.

Claim 13

A CMOS differential amplifier circuit as claimed in claim 10 wherein the channel regions of said two current sourcing transistors and said first and second control transistors are of one conductivity type and wherein the channel regions of said two amplifier transistors, said current sinking transistor, and said third control transistor are of a second conductivity type.

Claim 14

A CMOS differential amplifier circuit as claimed in claim 11 wherein said first conductivity type is P channel and said second conductivity type is N channel.

Claim 15

A CMOS differential amplifier circuit including a first and second branch circuit, said amplifier circuit comprising: a first CMOS amplifier transistor comprising a source, a drain and a gate, the source to drain circuit thereof being in said first branch circuit of said amplifier, a second CMOS amplifier transistor comprising a source, a drain, and a gate, the source to drain circuit thereof being in said second branch circuit of said amplifier parallel to said first branch circuit, a CMOS current sourcing transistor having a source, a drain, and a gate, the source to drain circuit thereof being coupled to the source to drain circuit of said first amplifier transistor in said first branch circuit, a CMOS current sinking transistor having a source, a drain, and a gate, the source to drain circuit thereof being coupled in common to the source to drain circuits of said two amplifier transistors, a source of electrical potential, said two branch circuits and the source to drain circuit of said current sinking transistor being coupled in series across said source of potential, and a CMOS control circuit for providing a first reference voltage to be applied to the gate of said current sourcing transistor and a second reference voltage to be applied to the gate of said current sinking transistor, said CMOS control circuit comprising: a first CMOS control transistor having a source, a drain, and a gate, a resistor circuit coupled in series with the source to drain circuit of said first control transistor across said source of potential, the gate of said first control transistor being coupled to the node of said resistor and said source to drain circuit of said first control transistor, the gate of said current sourcing transistor being coupled to said node whereby the voltage developed at said node is utilized as the first reference voltage to the gate of said current sourcing transistor, a second CMOS control transistor comprising a source, a drain, and a gate, the gate thereof being coupled to the node of said resistor and said source to drain circuit of said first control transistor whereby said first reference voltage is applied to the gate of said second control transistor, and a third CMOS control transistor having a source, a drain, and a gate, the source to drain circuit of said third control transistor being coupled in series with the source to drain circuit of said second control transistor across said source of potential, the gate of said third control transistor being coupled to the node of the source to drain circuits of said second control transistor and said third control transistor, the gate of said current sinking transistor being coupled to the node of said source to drain circuits of said second and third control transistors whereby the voltage developed at said node is utilized as the second reference voltage to the gate of said current sinking transistor, the dimensions of the current sourcing transistor and the first control transistor being such that the current sourcing transistor limits at a current of ##EQU5## when the length of the channel regions of the current sourcing transistor and the first control transistor are equal and where W c . source is the channel width for the current source transistor, W F .C. is the channel width for said first control transistor, V R1 is the first reference voltage, and R is the value of the resistor, and the dimensions of the first, second, and third control transistors and the current sinking transistor being such that the current sinking transistor limits at a current of ##EQU6## when the lengths of the channel regions of the first and second control transistors are equal and the lengths of the channel regions of the third control transistor and the current sinking transistor are equal and where W S .C. is the channel width for the second control transistor, W C .SINK is the channel width for the current sinking transistor, and W T .C. is the channel width for the third control transistor.

Claim 16

A CMOS differential amplifier circuit including a first and second branch circuit, said amplifier circuit comprising: a first CMOS amplifier transistor comprising a source, a drain and a gate, the source to drain circuit thereof being in said first branch circuit of said amplifier, a second CMOS amplifier transistor comprising a source, a drain, and a gate, the source to drain circuit thereof being in said second branch circuit of said amplifier parallel to said first branch circuit, a CMOS current sourcing transistor having a source, a drain, and a gate, the source to drain circuit thereof being coupled to the source to drain circuit of said first amplifier transistor in said first branch circuit, a CMOS current sinking transistor having a source, a drain, and a gate, the source to drain circuit thereof being coupled in common to the source to drain circuits of said two amplifier transistors, a source of electrical potential, said two branch circuits and the source to drain circuit of said current sinking transistor being coupled in series across said source of potential, and a CMOS control circuit for providing a first reference voltage to be applied to the gate of said current sourcing transistor and a second reference voltage to be applied to the gate of said current sinking transistor, said CMOS control circuit comprising: a first CMOS control transistor having a source, a drain, and a gate, a resistor circuit coupled in series with the source to drain circuit of said first control transistor across said source of potential, the gate of said first control transistor being coupled to the node of said resistor and said source to drain circuit of said first control transistor, the gate of said current sourcing transistor being coupled to said node whereby the voltage developed at said node is utilized as the first reference voltage to the gate of said current sourcing transistor, a second CMOS control transistor comprising a source, a drain, and a gate, the gate thereof being coupled to the node of said resistor and said source to drain circuit of said first control transistor whereby said first reference voltage is applied to the gate of said second control transistor, and a third CMOS control transistor having a source, a drain, and a gate, the source to drain circuit of said third control transistor being coupled in series with the source to drain circuit of said second control transistor across said source of potential, the gate of said third control transistor being coupled to the node of the source to drain circuits of said second control transistor and said third control transistor, the gate of said current sinking transistor being coupled to the node of said source to drain circuits of said second and third control transistors whereby the voltage developed at said node is utilized as the second reference voltage to the gate of said current sinking transistor, the dimensions of the current sourcing transistor and the first control transistor being such that the current sourcing transistor limits at a current of ##EQU5## when the length of the channel regions of the current sourcing transistor and the first control transistor are equal and where W c . source is the channel width for the current source transistor, W F .C. is the channel width for said first control transistor, V R1 is the first reference voltage, and R is the value of the resistor, and the dimensions of the first, second, and third control transistors and the current sinking transistor being such that the current sinking transistor limits at a current of ##EQU6## when the lengths of the channel regions of the first and second control transistors are equal and the lengths of the channel regions of the third control transistor and the current sinking transistor are equal and where W S .C. is the channel width for the second control transistor, W C .SINK is the channel width for the current sinking transistor, and W T .C. is the channel width for the third control transistor.

Claim 17

A CMOS differential amplifier circuit as claimed in claim 13 wherein the channel region of said current sourcing transistor and said first and second control transistors are of one conductivity type and wherein the channel regions of said two amplifier transistors, said current sinking transistor, and said third control transistor are of a second conductivity type.

Claim 18

A CMOS differential amplifier circuit as claimed in claim 14 wherein said first conductivity type is P channel and said second conductivity type is N channel.

Claim 19

A CMOS differential amplifier circuit as claimed in claim 13 including a second CMOS current sourcing transistor having a source, a drain, and a gate, the source to drain circuit thereof being coupled to the source to drain circuit of said second amplifier transistor in said second branch circuit, the gate thereof being coupled to said node of said resistor and said source to drain circuit of said first control transistor, the length and width of the channel region of said second current sourcing transistor being substantially equal to the length and width, respectively, of the channel region of said first current sourcing transistor.

Claim 20

A CMOS differential amplifier circuit as claimed in claim 16 wherein the channel regions of said two current sourcing transistors and said first and second control transistors are of one conductivity type and wherein the channel regions of said two amplifier transistors, said current sinking transistor and said third control transistor are of a second conductivity type.

Claim 21

A CMOS differential amplifier circuit as claimed in claim 17 wherein said first conductivity type is P channel and said second conductivity type is N channel.