Fabrication of matched complementary transistors in integrated circuits

Claim 1

A process for providing matched complementary transistors in an integrated circuit, which comprises: partially diffusing a first impurity of one conductivity-determining type into a first collector region of opposite conductivity type extending to a major planar surface of a body of single crystal material to form a first base region extending to said surface within said first collector region, said first impurity having a relatively slow diffusion coefficient in said single crystal material, partially diffusing a second impurity of said opposite conductivity-determing type having a relatively faster diffusion coefficient in said crystal material into a second collector region of said one conductivity type extending to said surface and spaced apart from said first collector region along said surface of said body to form a second base region extending to said surface within said second collector region, while simultaneously increasing the depth of penetration of said first impurity in said first collector region, partially diffusing another portion of said second impurity into said first region to form a first emitter region extending to said surface within said first base region, while simultaneously increasing the depth of penetration of said first and second impurities in the first and second collector regions, respectively, and diffusing a third impurity of said one conductivitydetermining type having a still faster diffusion coefficient in said single crystal material into said second base region to form a second emitter region extending to said surface within said second base region, while simultaneously increasing the depth of penetration of said first and second impurities in the first and second collector regions and in the first base region, respectively, said diffusing steps being performed at temperatures and for times sufficient to produce substantially equal final base-collector junction depths from said surface, and substantially equal base-emitter junction depths from said surface, within said first and second collector regions.

Claim 14

A method of fabricating complementary semiconductor devices in a monolithic substrate, which comprises: sequentially introducing a plurality of different conductivity-determining impurities having different diffusion coefficients into two spaced-apart single crystal semiconductor segments of opposite conductivity type in said substrate, diffusing each introduced impurity in the sequence into its respective single crystal semiconductor segment at a temperature and for a period sufficient to obtain at least partial diffusion of that impurity toward a desired depth in the respective single crystal semiconductor segment while simultaneously diffusing each earlier-introduced impurity further toward a final desired depth in the respective segment, until predetermined substantially common junction depths are attained between corresponding operational regions of the two segments to form matched complementary devices.

Claim 15

A method of fabricating complementary semiconductor devices in a monolithic substrate, which comprises: sequentially introducing a plurality of different conductivity-determining impurities having different diffusion coefficients into two spaced-apart single crystal semiconductor segments of opposite conductivity type in said substrate, diffusing each introduced impurity in the sequence into its respective single crystal semiconductor segment at a temperature and for a period sufficient to obtain at least partial diffusion of that impurity toward a desired depth in the respective single crystal semiconductor segment while simultaneously diffusing each earlier-introduced impurity further toward a final desired depth in the respective segment, until predetermined substantially common junction depths are attained between corresponding operational regions of the two segments to form matched complementary devices.