Vehicle speed control circuit

Claim 2

In a vehicle having a source of a pulsed vehicle road speed signal of a frequency proportional to the vehicle road speed and a throttle control means, a speed control circuit for automatically maintaining the speed of the vehicle at a desired road speed, comprising: means actuated by the vehicle operator when the vehicle reaches the desired road speed and responsive to the first vehicle road speed signal pulse to occur after said actuation for generating a first signal having a magnitude which is a function of the time elapsed from the occurrence of said first pulse; means responsive to said first pulse generating a second signal having a magnitude which is a different function of the time elapsed from the occurence of said first pulse; means for comparing the magnitudes of said first and second signals and for terminating the generation of said first signal when said magnitudes coincide wherein said means for generating said first signal stores said first signal as the desired road speed signal; and comparator and control signal generating means responsive to the vehicle road speed signal and said desired road speed signal for generating a control signal to have the throttle control means to maintain the speed of the vehicle at the desired road speed.

Claim 3

A speed control circuit according to claim 1 wherein said means for generating a first signal includes an oscillator for generataing a relatively high frequency pulse train; a binary counter for counting the pulses of said pulse train and for generating a binary coded output signal representing the accumulated total pulse count; and a digital to analog converter for continuously converting said binary coded output signal into said first signal having a magnitude proportional to the accumulated total pulse count.

Claim 4

A speed control circuit according to claim 1 wherein said means for generating a second signal includes a capacitor connected to the pulsed vehicle road speed signal source and responsive to said pulses for generating said second signal as a D.C. voltage having a magnitude proportional to the vehicle road speed capped by a triangular waveform having each positive slope initiated at the leading edge of one of said pulses.

Claim 5

In a vehicle having a source of a pulsed vehicle road speed signal of a frequency proportional to the vehicle road speed and a throttle control means, a speed control circuit for automatically maintaining the speed of the vehicle at a desired road speed, comprising: a set point means actuated by the vehicle operator when the vehicle reaches the desired road speed and responsive to the first vehicle road speed signal pulse to occur after said actuation for generating a set signal; means responsive to said set signal for generating a first signal having a magnitude which is a function of the time elapsed from the occurrence of said first pulse; means responsive to said first pulse for generating a second signal having a magnitude which is a different function of the time elapsed from the occurrence of said first pulse; means for comparing the magnitudes of said first and second signals and for generating a reset signal when the magnitudes coincide wherein said means for generating said first signal is responsive to said reset signal to terminate the generation of said first signal and includes means to store said first signal as the desired road speed signal; and comparator and control signal generating means responsive to the vehicle road speed signal and said desired road speed signal for generating a duty cycle modulated control signal to the throttle control means to maintain the speed of the vehicle at the desired road speed.

Claim 6

In a vehicle having a source of a pulsed vehicle road speed signal of a frequency proportional to the vehicle road speed and a throttle control means, a speed control circuit for automatically maintaining the speed of the vehicle at a desired road speed, comprising: a set point means actuated by the vehicle operator when the vehicle reaches the desired road speed and responsive to the first vehicle road speed signal pulse to occur after said actuation for generating a set signal; means responsive to said set signal for generating a first signal having a magnitude which is a function of the time elapsed from the occurrence of said first pulse; means responsive to said first pulse for generating a second signal having a magnitude which is a different function of the time elapsed from the occurrence of said first pulse; means for comparing the magnitudes of said first and second signals and for generating a reset signal when the magnitudes coincide wherein said means for generating said first signal is responsive to said reset signal to terminate the generation of said first signal and includes means to store said first signal as the desired road speed signal; and comparator and control signal generating means responsive to the vehicle road speed signal and said desired road speed signal for generating a duty cycle modulated control signal to the throttle control means to maintain the speed of the vehicle at the desired road speed.

Claim 7

A speed control circuit according to claim 4 wherein said set point means includes a set point switch; means responsive to the actuation of said set point switch and to the first vehicle road speed signal pulse to occur after said actuation for generating said set signal; and means responsive to said set signal for inhibiting said means for generating said set signal from responding to a subsequent vehicle road speed pulse.

Claim 8

A speed control circuit according to claim 5 wherein said means for inhibiting inhibits said means for generating said set point signal during a predetermined time delay.

Claim 9

A speed control circuit according to claim 4 wherein said means for generating said first signal includes a set point latch responsive to said set signal for generating an output signal, pulse generating means responsive to said output signal for generating a train of pulses at a relatively high frequency and means for continuously converting a binary coded signal into said first signal with a magnitude proportional to an accumulated total pulse count and wherein said means to store is a counter for counting the pulses of said pulse train and for continuously generating said binary coded signal representing the accumulated total pulse count.

Claim 10

A speed control circuit according to claim 7 wherein said set point latch is responsive to said reset signal for removing said set point latch output signal from said pulse generating means.

Claim 11

A speed control circuit according to claim 4 including an anticipatory control means responsive to said set signal for removing the vehicle road speed from said comparator and control signal means to drive said control signal to a 100 percent duty cycle to pre-position the throttle of the vehicle.

Claim 12

In a vehicle having a source of a vehicle road speed signal and a throttle control means, a speed control circuit for automatically maintaining the speed of the vehicle at a desired road speed, comprising: means actuated by the vehicle operator when the vehicle reaches the desired road speed for generating a desired road speed signal; comparator and control signal generating means responsive to the vehicle road speed signal and said desired road speed signal for generating a duty cycle modulated control signal to the throttle control means to maintain the speed of the vehicle at the desired road speed; and anticipatory control means responsive to said actuation of said means for generating a desired road speed signal for removing the vehicle road speed signal from an input of said comparator and control signal means to drive said control signal to a 100 percent duty cycle to pre-position the throttle of the vehicle.

Claim 13

In a vehicle having a source of a vehicle road speed signal and a throttle control means, a speed control circuit for automatically maintaining the speed of the vehicle at a desired road speed, comprising: means actuated by the vehicle operator when the vehicle reaches the desired road speed for generating a desired road speed signal; comparator and control signal generating means responsive to the vehicle road speed signal and said desired road speed signal for generating a duty cycle modulated control signal to the throttle control means to maintain the speed of the vehicle at the desired road speed; and anticipatory control means responsive to said actuation of said means for generating a desired road speed signal for removing the vehicle road speed signal from an input of said comparator and control signal means to drive said control signal to a 100 percent duty cycle to pre-position the throttle of the vehicle.

Claim 14

A speed control circuit according to claim 10 wherein said means for generating a desired road speed signal includes means for generating an output signal having a magnitude which is a function of the time elapsed from the actuation of said anticipatory control means; comparator means responsive to said output signal and the vehicle road speed signal for generating a reset signal when the magnitudes are equal and wherein said anticipatory control means is responsive to said reset signal to replace the vehicle road speed signal at said input of said comparator and control signal means.