Vehicle speed control

Claim 2

In a vehicle speed control, the combination comprising: means for providing a speed signal proportional to vehicle speed; a pulse source; a digital counter for counting said pulses; a network associated with said counter for producing a reference signal proportional to the count stored in said counter; a comparator responsive to matching of said reference signal and speed signal for generating a comparator signal; a manually actuable switch; a reset unit responsive to actuation of said switch for resetting said counter and for generating a reset signal; a gate responsive to said reset signal for conducting pulses from source to said counter and responsive to said comparator signal for isolating said counter from said source; means responsive to the relationship of said speed signal and reference signal for adjusting vehicle speed to adjust said relationship to a desired condition.

Claim 3

a first NAND gate connected at one input thereof to said pulse means and at an output thereof to said memory means, and

Claim 4

a first NAND gate connected at one input thereof to said pulse means and at an output thereof to said memory means, and

Claim 5

In a vehicle speed control, the combination comprising: means for providing a speed signal proportional to vehicle speed; a pulse source; a digital counter for counting said pulses; a network associated with said counter for producing a reference signal proportional to the count stored in said counter; a comparator responsive to matching of said reference signal and speed signal for generating a comparator signal; a manually actuable switch; a reset unit responsive to actuation of said switch for resetting said counter and for generating a reset signal; a gate responsive to said reset signal for conducting pulses from source to said counter and responsive to said comparator signal for isolating said counter from said source; means responsive to the relationship of said speed signal and reference signal for adjusting vehicle speed to adjust said relationship to a desired condition.

Claim 6

In a vehicle speed control, the combination comprising: means for providing a speed signal proportional to vehicle speed; a pulse source; a digital counter for counting said pulses; a network associated with said counter for producing a reference signal proportional to the count stored in said counter; a comparator responsive to matching of said reference signal and speed signal for generating a comparator signal; a manually actuable switch; a reset unit responsive to actuation of said switch for resetting said counter and for generating a reset signal; a gate responsive to said reset signal for conducting pulses from source to said counter and responsive to said comparator signal for isolating said counter from said source; means responsive to the relationship of said speed signal and reference signal for adjusting vehicle speed to adjust said relationship to a desired condition.

Claim 7

The apparatus defined in claim 1 in which said means responsive to the relationship of said speed signal and said reference signal comprises: a differential amplifier, said differential amplifier having an output variable in response to variation of said speed signal with respect to said reference signal, a pulse width modulator responsive to said differential amplifier for producing a variable duty cycle pulse train, the duty cycle of said pulse width modulator varying in relation to the said output of said differential amplifier; and servo means adapted to vary the power setting of the vehicle in proportion to the length of said duty cycle.

Claim 8

enabling gating means interposed between another input of said first NAND gate and said comparator means for applying an inhibiting potential to said another input in response to said correspondence signal to disable said first NAND gate from conduction of said pulses to said memory means; F. power regulating means for changing the power setting of said vehicle; and G. control means responsive tO subsequent changes in the correspondence between said speed and reference signals for adjusting said power regulating means in a manner to maintain said correspondence.

Claim 9

enabling gating means interposed between another input of said first NAND gate and said comparator means for applying an inhibiting potential to said another input in response to said correspondence signal to disable said first NAND gate from conduction of said pulses to said memory means; F. power regulating means for changing the power setting of said vehicle; and G. control means responsive tO subsequent changes in the correspondence between said speed and reference signals for adjusting said power regulating means in a manner to maintain said correspondence.

Claim 10

The apparatus defined in claim 2 in which said pulse width modulator comprises a fixed frequency oscillator having a narrow width pulse output and a monostable multivibrator having a first state initiated by said oscillator and a second state; and means connecting the output of said differential amplifier to said monostable multivibrator for causing same to assume said second state after a period related to said differential amplifier output whereby to determine the length of said duty cycle.

Claim 11

The apparatus defined in claim 2 in which said speed signal providing means comprises a source responsive to a vehicle speed and a first operational amplifier responsive thereto; said differential amplifier comprises a second operational amplifier to which said speed signal and reference signal are applied and having an output variable in response to differences therebetween; and said comparator circuit comprises a third operational amplifier responsive also to said speed signal and reference signal, said first and second operational amplifiers having feedback means to maintain the gain thereof at a level substantially less than that of said third operational amplifier, whereby said third operational amplifier provides a discrete two- level alternative output instead of the continuously variable output of said first and second operational amplifiers.

Claim 12

In a vehicle speed control apparatus, the combination comprising: A. pulse means; B. memory means for counting said pulses and storing said count; C. gate means connected at one input thereof to said pulse means and at an output thereof to said counting means; D. means producing a vehicle speed signal; E. comparator means producing an inhibit signal in response to a preselected correspondence between said count and said vehicle speed signal; F. means applying said inhibit signal to another input of said gate for disabling conduction of said pulses to said counting means; G. power regulating means for changing the power setting of said vehicle; and H. control means responsive to subsequent changes in the correspondence between said count and said vehicle speed signal for adjusting said power regulating means in a manner to maintain said correspondence.

Claim 13

In a vehicle speed control apparatus, the combination comprising: A. pulse means; B. memory means for counting said pulses and storing said count; C. gate means connected at one input thereof to said pulse means and at an output thereof to said counting means; D. means producing a vehicle speed signal; E. comparator means producing an inhibit signal in response to a preselected correspondence between said count and said vehicle speed signal; F. means applying said inhibit signal to another input of said gate for disabling conduction of said pulses to said counting means; G. power regulating means for changing the power setting of said vehicle; and H. control means responsive to subsequent changes in the correspondence between said count and said vehicle speed signal for adjusting said power regulating means in a manner to maintain said correspondence.

Claim 14

The apparatus of claim 5 including means manually operable for preventing said counting by said memory means.

Claim 15

The apparatus defined in claim 5, in which said vehicle speed signal means comprises means for producing an a.c. speed signal proportional to instantaneous vehicle speed; and including frequency-to-voltage converter means responsive to said a.c. speed signal for producing a d.c. speed signal of amplitude proportional to instantaneous vehicle speed.

Claim 16

The apparatus defined in claim 7, in which said frequency-to-voltage converter means comprises: transistor switching means energizable by said a.c. speed signal; an RC network responsive to actuation of said transistor switching means for producing a d.c. signal proportional in amplitude to the frequency of said a.c. speed signal; and an operational amplifier responsive to said d.c. signal for producing said d.c. speed signal.

Claim 17

The apparatus defined in claim 5 wherein said gate means comprises: a first NAND gate connected at one input thereof to said pulse providing means and at an output thereof to said memory means; and enabling gating means interposed between another input of said first NAND gate and said comparator means for applying said inhibiting signal to said another input in response to sensing by said comparator means of said preselected correspondence to disable said first NAND gate from conduction of said pulse train therethrough.

Claim 18

The apparatus defined in claim 5 including reset means responsive to manual actuation by the vehicle operator for applying a reset signal to said memory means for resetting same at a minimum count level.

Claim 19

The apparatus defined in claim 10 in which said enabling gating means comprises: a second NAND gate having an output connected to said another input of said first NAND gate; a third NAND gate having an input connected to said output of said second NAND gate and an output connected to an input of said second NAND gate, said second NAND gate having a further input connected to said reset means and said third NAND gate having a further input connected to said comparator means.

Claim 20

The apparatus defined in claim 5 in which said memory means comprises means responsive to the count stored for producing a d.c. voltage proportional in amplitude to said count and for applying said d.c. signal to said comparator means.

Claim 21

The apparatus defined in claim 12 wherein said memory means comprises a series of flip-flops, an output of each of said flip-flop connecting to an input of the next succeeding one of said flip-flops, the initial one of said flip-flops being connected to said pulse providing means; said d.c. reference signal producing means including a first voltage divider connected between a fixed potential point and an output point and a plurality of further voltage dividers each connected at one end thereof to a source of potential different from said fixed potential, intermediate the ends thereof to an output of a respective one of said flip-flops and at the remaining ends thereof being connected to points spaced along the intermediate portion of said first-mentioned voltage divider, said spaced points being in a sequence corresponding to the sequence of flip-flops, whereby a rising count in said memory means results in a rising potential on said output point whereby upcounting of said memory means results in a stepwise potential rise on said output point; and current supply means responsive to the potential on said output point for generating said reference signal in correspondence thereto.

Claim 22

The apparatus defined in claim 5 in which said comparator means comprises high gain d.c. amplifier means, having a first input connected to said speed signal providing means and a second input connected to said memory means, for providing a rapid, large potential change at the output thereof in response to unidirectional approach of said reference signal toward the potential of said speed signal; switching means responsive to said change of output of said amplifier means for switching to a state indicating a matched condition of said speed and reference signals and thereby for deactuating said gate means to stabilize the value of said reference signal.

Claim 23

The apparatus defined in claim 14 in which said amplifier means comprises an operational amplifier arranged for high gain, the speed and reference signal inputs thereto being arranged to provide a drop in operational amplifier output as the reference signal steps up to the level of the speed signal; and said switching means comprises first and second transistors sequentially responsive to said drop for switching the potential applied thereby to said gate means for disabling same.

Claim 24

The apparatus defined in claim 5 in which said control means comprises differential means responsive to differentials between said speed and reference signals; two-state means periodically switched to a first state and means responsive to said differential means for switching to a second state after a time controlled by said differential means; said power regulating means being responsive to one of said first and second states of said two-state means for controlling vehicle power in accordance with the time length thereof.

Claim 25

The apparatus defined in claim 16 in which said two-state means comprises a monostable multivibrator having first and second valve means each having output electrodes and a control electrode, capacitive means connecting the output electrode of one of said valves to the control terminal of the other of said valves, means applying charging potential to one side of said capacitive means and means coupled to said differential means for applying a bias signal responsive to changes in the relationship between said speed and reference signals to the other side of said capacitive means, so that the time required to charge said capaciTive means sufficiently to change the state of said second valve is related to the relationship of said speed and reference signals.

Claim 26

The apparatus defined in claim 5 including switch means responsive to manual actuation for enabling said power regulating means to change the power setting of said vehicle in response to adjustment of said power regulating means by said control means; reset means responsive to actuation of said switch means for enabling said gate means to supply pulses to said memory means and for holding said memory means at a minimum count level.

Claim 27

The apparatus defined in claim 18 in which said switch means has first contact means actuable for enabling of said power regulating means and second contact means connected to said reset means and deactuable for returning control of said gate means to said comparator means and for allowing pulse accumulation by said memory means when said comparator means allows conduction of said gate means thereto.

Claim 28

The apparatus defined in claim 5 including means energizable for enabling said power regulating means to change the power setting of said vehicle in response to adjustment by said control means; a manually actuable switch; inhibit means responsive to a speed signal above a preselected level for enabling energization of said enabling means upon actuation of said manually actuable switch.

Claim 29

The apparatus defined in claim 20 in which said inhibit means includes a Zener diode to which a signal proportional to said speed signal is applied, the Zener voltage of which is selected to allow Zener conduction when the vehicle speed exceeds a predetermined minimum limit; and means responsive to conduction of said Zener diode for enabling energization of said enabling means upon actuation of said manually actuable switch.

Claim 30

The apparatus defined in claim 20 including brake switch means openable in response to actuation of the vehicle brake; a lock-in contact in series therewith and with said enabling means and responsive to actuation of said enabling means for closing; a source of potential connected to said enabling means through said brake switch and said lock-in contact for energizing same, whereby actuation of the vehicle brake will open said brake switch and de-energize said enabling means; resume switch means paralleling said brake switch means and lock-in contact and manually closable for energizing said enabling means to return control of the vehicle speed to said power regulating means subsequent to actuation of the vehicle brake.

Claim 31

A vehicle speed control for maintaining the vehicle at a preselected speed, said control comprising: A. means to produce pulses; B. means for counting said pulses and producing a first voltage representative of the number of pulses counted; C. means for producing a second voltage representative of vehicle speed; D. means for stopping the passage of said pulses to said counting means when said first and second voltages are substantially equal; E. difference means for producing a third voltage representative of the difference between said first and second voltages; F. two state means periodically switched to a first state, and then to a second state after a time controlled by said third voltage; and G. means responsive to one of said first and second states for controlling the speed of said vehicle.

Claim 32

A vehicle speed control for maintaining the vehicle at a preselected speed, said control comprising: A. means to produce pulses; B. means for counting said pulses and producing a first voltage representative of the number of pulses counted; C. means for producing a second voltage representative of vehicle speed; D. means for stopping the passage of said pulses to said counting means when said first and second voltages are substantially equal; E. difference means for producing a third voltage representative of the difference between said first and second voltages; F. two state means periodically switched to a first state, and then to a second state after a time controlled by said third voltage; and G. means responsive to one of said first and second states for controlling the speed of said vehicle.

Claim 33

The speed control of claim 23, wherein said stopping means comprises: A. means for producing a first signal when said second voltage is greater than said first voltage and a second signal when said second voltage is less than said first voltage; and B. means allowing the passage of said pulses to said counting means when said first signal is produced and preventing said passage when said second signal is produced.

Claim 34

Apparatus actuable for automatically controlling the speed of a vehicle comprising: A. speed signal means for providing a spEed signal related to instantaneous vehicle speed; B. memory means for accumulating pulses for generating a reference signal corresponding to said pulse accumulation; C. gate means positioned ahead of said memory means and deactuable for preventing further pulse accumulation by said memory means; D. pulse means supplying a train of pulses to said memory means; E. comparator means responsive to a preselected correspondence between said speed signal and reference signal for deactuating said gate means whereby the output of said memory means stabilizes and becomes a reference standard; F. differential means responsive to differentials between said speed and reference signals; G. first and second state means comprising a monostable multivibrator having first and second valve means each having an output electrode and a control electrode, capacitive means connecting the output electrode of one of said valves to the control electrode of the other of said valves, means applying a changing potential to one side of said capacitive means and means coupled to said differential means for applying a bias signal responsive to changes in the relationship between said speed and reference signals to the other side of said capacitive means, whereby said first and second state means is switched to one of said two states in response to the time required to charge said capacitive means sufficiently to change the state of said second valve as a function of the relationship between said speed and reference signals; and H. power regulating means responsive to said first and second states for controlling the power setting of said vehicle.

Claim 35

Apparatus actuable for automatically controlling the speed of a vehicle comprising: A. speed signal means for providing a spEed signal related to instantaneous vehicle speed; B. memory means for accumulating pulses for generating a reference signal corresponding to said pulse accumulation; C. gate means positioned ahead of said memory means and deactuable for preventing further pulse accumulation by said memory means; D. pulse means supplying a train of pulses to said memory means; E. comparator means responsive to a preselected correspondence between said speed signal and reference signal for deactuating said gate means whereby the output of said memory means stabilizes and becomes a reference standard; F. differential means responsive to differentials between said speed and reference signals; G. first and second state means comprising a monostable multivibrator having first and second valve means each having an output electrode and a control electrode, capacitive means connecting the output electrode of one of said valves to the control electrode of the other of said valves, means applying a changing potential to one side of said capacitive means and means coupled to said differential means for applying a bias signal responsive to changes in the relationship between said speed and reference signals to the other side of said capacitive means, whereby said first and second state means is switched to one of said two states in response to the time required to charge said capacitive means sufficiently to change the state of said second valve as a function of the relationship between said speed and reference signals; and H. power regulating means responsive to said first and second states for controlling the power setting of said vehicle.

Claim 36

In a vehicle speed control, the combination comprising: A. means of providing a speed signal proportional to vehicle speed; B. a pulse source; C. a digital counter for counting said pulses; D. a network associated with said counter for producing a reference signal proportional to the count stored in said counter; E. a comparator responsive to matching of said reference signal and speed signal for generating a comparator signal; F. a manually actuable switch; G. a reset unit responsive to actuation of said switch for resetting said counter and for generating a reset signal; H. a gate responsive to said reset signal for conducting pulses from said source to said counter and responsive to said comparator signal for isolating said counter from said source; I. means producing a variable amplitude signal in response to a difference between said speed and reference signals; J. means producing a variable duty cycle pulse train having a duty cycle length proportional to the amplitude of said variable amplitude signal; and K. means adapted to vary the power setting of the vehicle in proportion to the length of said duty cycle pulses.

Claim 37

In a vehicle speed control, the combination comprising: A. means of providing a speed signal proportional to vehicle speed; B. a pulse source; C. a digital counter for counting said pulses; D. a network associated with said counter for producing a reference signal proportional to the count stored in said counter; E. a comparator responsive to matching of said reference signal and speed signal for generating a comparator signal; F. a manually actuable switch; G. a reset unit responsive to actuation of said switch for resetting said counter and for generating a reset signal; H. a gate responsive to said reset signal for conducting pulses from said source to said counter and responsive to said comparator signal for isolating said counter from said source; I. means producing a variable amplitude signal in response to a difference between said speed and reference signals; J. means producing a variable duty cycle pulse train having a duty cycle length proportional to the amplitude of said variable amplitude signal; and K. means adapted to vary the power setting of the vehicle in proportion to the length of said duty cycle pulses.