US3891046A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital speed control
Assignee: Northrop Grumman Space and Mission Systems Corp
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Filing: 1972-02-03
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Granted: 1975-06-24
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Expires: 1992-02-03
Abstract
Abstract A digital system for maintaining the speed of a motor vehicle at a preselected speed is disclosed wherein a desired vehicle speed is set into a digital memory bank. The instantaneous actual speed of the vehicle is determined by a digital readout. The desired vehicle speed and the actual speed of the vehicle are compared to produce a digital error signal which is used to control the throttle setting of the vehicle so that the actual speed of the vehicle equals the desired speed.
Inventors
- 👤 Jeffrey A Oicles
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 22:47
CPC Classifications
F; F02; F02D; F02D31/00; F02D31/001; F02D31/002; B; B60; B60K; B60K31/00; B60K31/02; B60K31/04; B60K31/042; B60K31/045; B60K31/047; H; H02; H02P; H02P23/00; H02P23/22; B60W; B60W2710/00; B60W2710/06; B60W2710/0644
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
520 words
A digital speed control for maintaining a motor vehicle at a preselected constant speed comprising: a. means for generating a first digital signal responsive to the actual speed of the vehicle comprising a series of speed signal pulses having a pulse repetition frequency proportional to the speed of the vehicle; b. means for generating a second digital signal responsive to a constant preselected vehicle speeD comprising a digital reference clock, a first digital counter and means for clocking said first digital counter in response to said first digital signal during a first given reference clock period, thereby storing in said first digital counter a first digital number responsive to the preselected speed of the vehicle; c. means for digitally comparing the first digital signal responsive to the actual speed of the vehicle and the second digital signal responsive to the constant preselected vehicle speed to produce a digital error signal comprising; d. second digital down counter means clocked by said first signal responsive to the actual speed of the vehicle; e. means for generating a first and a second timing pulse at the beginning of each reference clock period; f. first AND gate means gating, upon receipt of a second timing pulse, the first digital number responsive to the speed of the vehicle stored in said first digital counter means to the second digital counter means, said second digital counter means being a down counter clocked by the first digital signal pulse train to count down for one reference clock period, so that if the actual speed of the vehicle is greater than the preselected speed of the vehicle the second counter will count down through zero, and if the actual speed of the vehicle is less than the preselected speed of the vehicle a second digital number will remain stored on the second digital counter; g. means for generating a ''''carry'''' signal when the second digital counter counts down through zero; h. binary means for dividing the first digital signal responsive to the actual speed of the vehicle; i. third digital counter means clocked by the divided binary signal responsive to the actual speed of the vehicle; j. second AND gate means gating, upon receipt of a first timing pulse, the second digital number stored in the second digital down counter to the third digital counter means, said third digital counter means being a down counter clocked by the divided binary signal responsive to the actual speed of the vehicle counting down during one reference clock period, so that if the actual speed of the vehicle is less than the preselected speed of the vehicle the third counter may count down through zero; k. third AND gate means producing an output whenever the third counter counts down through zero; l. means for producing a pulse width modulated error signal having a pulse width proportional to the difference in speed between the preselected constant speed and an actual vehicle speed lower than the preselected speed; and m. means for adjusting the speed of the vehicle in response to said pulse width modulated error signal to maintain the preselected constant speed.
Claim 2
Dependent Claim
520 words
A digital speed control for maintaining a motor vehicle at a preselected constant speed comprising: a. means for generating a first digital signal responsive to the actual speed of the vehicle comprising a series of speed signal pulses having a pulse repetition frequency proportional to the speed of the vehicle; b. means for generating a second digital signal responsive to a constant preselected vehicle speeD comprising a digital reference clock, a first digital counter and means for clocking said first digital counter in response to said first digital signal during a first given reference clock period, thereby storing in said first digital counter a first digital number responsive to the preselected speed of the vehicle; c. means for digitally comparing the first digital signal responsive to the actual speed of the vehicle and the second digital signal responsive to the constant preselected vehicle speed to produce a digital error signal comprising; d. second digital down counter means clocked by said first signal responsive to the actual speed of the vehicle; e. means for generating a first and a second timing pulse at the beginning of each reference clock period; f. first AND gate means gating, upon receipt of a second timing pulse, the first digital number responsive to the speed of the vehicle stored in said first digital counter means to the second digital counter means, said second digital counter means being a down counter clocked by the first digital signal pulse train to count down for one reference clock period, so that if the actual speed of the vehicle is greater than the preselected speed of the vehicle the second counter will count down through zero, and if the actual speed of the vehicle is less than the preselected speed of the vehicle a second digital number will remain stored on the second digital counter; g. means for generating a ''''carry'''' signal when the second digital counter counts down through zero; h. binary means for dividing the first digital signal responsive to the actual speed of the vehicle; i. third digital counter means clocked by the divided binary signal responsive to the actual speed of the vehicle; j. second AND gate means gating, upon receipt of a first timing pulse, the second digital number stored in the second digital down counter to the third digital counter means, said third digital counter means being a down counter clocked by the divided binary signal responsive to the actual speed of the vehicle counting down during one reference clock period, so that if the actual speed of the vehicle is less than the preselected speed of the vehicle the third counter may count down through zero; k. third AND gate means producing an output whenever the third counter counts down through zero; l. means for producing a pulse width modulated error signal having a pulse width proportional to the difference in speed between the preselected constant speed and an actual vehicle speed lower than the preselected speed; and m. means for adjusting the speed of the vehicle in response to said pulse width modulated error signal to maintain the preselected constant speed.
Claim 3
Dependent Claim
73 words
A digital speed control as claimed in claim 1 wherein the means for producing the pulse width modulated error signal comprises: means for producing a first voltage at times corresponding to one speed signal pulse after the beginning of the second reference clock period; means for inhibiting the first voltage if a carry signal is produced; and means for inhibiting the first voltage in response to an output from the third AND gate.
Claim 4
Dependent Claim
85 words
A digital speed control as claimed in claim 1 wherein the means for producing the pulse width modulated error signal comprises: a first resetable digital flip-flop having an output times means for setting said first flip-flop at times corresponding to one speed signal pulse after the beginning of the second reference clock period; means for inhibiting the setting of said first flip-flop if a carry signal is produced, and means for resetting said first flip-flop in response to an output from said third AND gate.
Claim 5
Dependent Claim
85 words
A digital speed control as claimed in claim 3 and further including: a second resetable digital flip-flop; a fourth AND gate, one input to said fourth AND gate being from the output of said first digital flip-flop, and The other input to said fourth AND gate being from the output of said second digital flip-flop; means for resetting said second flip-flop in response to a command to disengage the speed maintaining system; and means for setting said second flip-flop to engage the speed maintaining system.
Claim 6
Dependent Claim
23 words
A digital speed control as claimed in claim 4 wherein the command to disengage the system is in response to a braking command.
Claim 7
Dependent Claim
40 words
A digital speed control as claimed in claim 5 wherein the means for adjusting the speed of the vehicle in response to the digital error signal comprises positioning a throttle to vary the speed of the motor of the vehicle.
Claim 8
Dependent Claim
517 words
A digital speed control for maintaining a motor vehicle at a preselected constant speed comprising: means for generating a first digital signal comprising a series of speed signal pulses having a pulse repetition frequency proportional to the actual speed of the vehicle; a digital reference clock; a first digital counter counting the number of speed signal pulses in one reference clock period to produce a first digital number proportional to a preselected speed of the vehicle during a first particular reference clock period; means for storing said first digital number responsive to the speed of the vehicle in said first digital counter; a second digital counter clocked by the first digital signal pulse train; means for generating a first timing pulse at the beginning of each reference clock period; means for generating a second timing pulse after the beginning of each reference clock period; a first AND gate gating, upon receipt of a second timing pulse, the first digital number responsive to the speed of the vehicle stored in said first digital counter to the second digital counter; said second digital counter being a down counter clocked by the first digital signal pulse train counting down for one reference clock period, so that if the actual speed of the vehicle is greater than the preselected speed of the vehicle the second counter will count down through zero, and if the actual speed of the vehicle is less than the preselected speed of the vehicle a second digital number will be stored on the second digital counter; means for generating a carry signal when said second digital counter counts down through zero; binary means for dividing the first digital signal responsive to the actual speed of the vehicle; a third digital counter clocked by the divided binary signal responsive to the actual speed of the vehicle; a second AND gate gating, upon receipt of a first timing pulse, the second digital number stored in the second digital down counter to the third digital counter; said third digital counter being a down counter, clocked by the divided binary signal responsive to the actual speed of the vehicle, counting down during one reference clock period, so that if the actual speed of the vehicle is less than the preselected speed of the vehicle the third counter may count down through zero; a third AND gate producing an output whenever the third counter counts down through zero; means for producing a pulse width modulated error signal having a width proportional to the difference in speed between the preselected constant speed and an actual vehicle speed lower than the preselected speed comprising: a first resetable digital flip-flop having an output; means for setting the first flip-flop in response to a first timing pulse; means for inhibiting the setting of the first flip-flop if a carry signal is produced, and means for resetting the first flip-flop in response to an output from the third AND gate; and means for adjusting the speed of the vehicle in response to the digital error signal, produced by the first flip-flop, to maintain the preselected constant speed.
Claim 9
Dependent Claim
517 words
A digital speed control for maintaining a motor vehicle at a preselected constant speed comprising: means for generating a first digital signal comprising a series of speed signal pulses having a pulse repetition frequency proportional to the actual speed of the vehicle; a digital reference clock; a first digital counter counting the number of speed signal pulses in one reference clock period to produce a first digital number proportional to a preselected speed of the vehicle during a first particular reference clock period; means for storing said first digital number responsive to the speed of the vehicle in said first digital counter; a second digital counter clocked by the first digital signal pulse train; means for generating a first timing pulse at the beginning of each reference clock period; means for generating a second timing pulse after the beginning of each reference clock period; a first AND gate gating, upon receipt of a second timing pulse, the first digital number responsive to the speed of the vehicle stored in said first digital counter to the second digital counter; said second digital counter being a down counter clocked by the first digital signal pulse train counting down for one reference clock period, so that if the actual speed of the vehicle is greater than the preselected speed of the vehicle the second counter will count down through zero, and if the actual speed of the vehicle is less than the preselected speed of the vehicle a second digital number will be stored on the second digital counter; means for generating a carry signal when said second digital counter counts down through zero; binary means for dividing the first digital signal responsive to the actual speed of the vehicle; a third digital counter clocked by the divided binary signal responsive to the actual speed of the vehicle; a second AND gate gating, upon receipt of a first timing pulse, the second digital number stored in the second digital down counter to the third digital counter; said third digital counter being a down counter, clocked by the divided binary signal responsive to the actual speed of the vehicle, counting down during one reference clock period, so that if the actual speed of the vehicle is less than the preselected speed of the vehicle the third counter may count down through zero; a third AND gate producing an output whenever the third counter counts down through zero; means for producing a pulse width modulated error signal having a width proportional to the difference in speed between the preselected constant speed and an actual vehicle speed lower than the preselected speed comprising: a first resetable digital flip-flop having an output; means for setting the first flip-flop in response to a first timing pulse; means for inhibiting the setting of the first flip-flop if a carry signal is produced, and means for resetting the first flip-flop in response to an output from the third AND gate; and means for adjusting the speed of the vehicle in response to the digital error signal, produced by the first flip-flop, to maintain the preselected constant speed.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-06-23 | 1978-12-23 | 1979-06-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-06-23 | 1982-12-23 | 1983-06-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-06-23 | 1986-12-23 | 1987-06-24 | $7700.00 | Window Closed / Lapsed |