Timer circuits

Claim 2

In a switching circuit of the kind employing a thyristor switch and means for producing trigger pulses at zero crossings of an alternating current signal to be switched, the improvement comprising, in combination: a counter having an initial count stored therein; means for deriving clock pulses from said trigger pulses for advancing the counter; circuit means initially in a first state and responsive to advancement of the count to a given value for changing to a second state; and logic gate means receptive of said trigger pulses and responsive to a selected state of said circuit means for applying said trigger pulses to said thyristor during the interval said circuit means is in said selected state.

Claim 3

The combination recited in claim 1 further comprising: initializing means responsive to a control signal for concurrently setting said counter to said initial count, for returning said circuit means to said first state and for preventing application of said trigger pulses to said thyristor.

Claim 4

The combination recited in claim 1 wherein said circuit means comprises: a programmable decoding gate receptive of selected ones of a plurality of logic output signals produced by said counter, said decoding gate being disabled when the count in said counter differs from a programmed value and being enabled when the count equals the programmed value.

Claim 5

The combination recited in claim 2 wherein said circuit means comprises: binary storage means coupled to said counter and to said initializing means for receiving set and reset input signals, respectively, and coupled to said logic gate means for supplying an output signal thereto of one value when set and of another value when reset.

Claim 6

The combination recited in claim 1 wherein: said counter includes a RESET input terminal, receptive of a first control signal, a CLOCK input terminal receptive of a clock input signal, and a plurality of output terminals producing output signals representative of the count stored therein; said circuit means comprises a multiple input logic gate having its input terminals connected to selected ones of the counter output terminals; said logic gate means comprises a two input gate connected at its output terminal to the gate electrode of said thyristor switch, said two input gate receiving said trigger pulses at one of its input terminals and connected at its other input terminal to the output terminal of said multiple input logic gate; and wherein said means deriving clock pulses for said counter comprises means coupling said CLOCK input terminal to said output terminal of said two input logic gate.

Claim 7

A timer circuit, comprising: two terminals for receiving an alternating current input signal; zero voltage detector means coupled to said two terminals for producing trigger pulses substantially at the axis crossings of said alternating current signal; a counter having an initial count stored therein and responsive to clock pulses for advancing the count, said clock pulses being derived from said trigger pulses; logic means coupled to said counter and initially in a first state, said logic means being responsive to the advancement of the count to a given value for changing to a second state; a triggerable electronic switch for connection in series with a load across said two terminals, said switch having a gate terminal for receiving said trigger pulses; and circuit means responsive to said trigger pulses and the state of said logic means for applying said trigger pulses to said gate terminal during the interval that said logic means is in a selected one of its states.

Claim 8

A timer circuit, comprising: two terminals for receiving an alternating current input signal; zero voltage detector means coupled to said two terminals for producing trigger pulses substantially at the axis crossings of said alternating current signal; a counter having an initial count stored therein and responsive to clock pulses for advancing the count, said clock pulses being derived from said trigger pulses; logic means coupled to said counter and initially in a first state, said logic means being responsive to the advancement of the count to a given value for changing to a second state; a triggerable electronic switch for connection in series with a load across said two terminals, said switch having a gate terminal for receiving said trigger pulses; and circuit means responsive to said trigger pulses and the state of said logic means for applying said trigger pulses to said gate terminal during the interval that said logic means is in a selected one of its states.

Claim 9

The timer circuit recited in claim 6 further comprising: initializing means responsive to a control signal for setting said counter to said initial count, for placing said logic means in said first state and for preventing application of said trigger pulses to said gate terminal.

Claim 10

The timer circuit recited in claim 7 wherein said triggerable electronic switch is selected from the group comprising thyristors, thyratrons and ignitrons.

Claim 11

The timer circuit recited in claim 6 wherein said logic means comprises: a programmable logic gate receptive of selected ones of a plurality of logic output signals produced by said counter, said programmable logic gate being disabled when the count in said counter differs from a programmed value and being enabled when the count equals the programmed value.

Claim 12

The timer circuit recited in claim 7 wherein said logic means comprises: binary storage means coupled to said counter and to said initializing means for receiving SET and RESET input signals, therefrom, respectively, and coupled to said circuit means for supplying an output signal thereto of one value when SET and of another value when RESET.