Poly-phase digital controller

Claim 1

A polyphase digital power control circuit in which polyphase power is controlled by binary counting technique which provides equal voltage loading of each phase comprising: a. a polyphase control transformer to provide appropriate input voltage with D.C. isolation and a minimum of phase distortion, b. zero crossing detectors to receive the input voltage from said polyphase control transformer and to produce a pulse output when the cyclic voltage appearing at theinput reverses its polarity, c. an OR gate to receive the pulse output from said said zero crossing and to produce a synchronizing pulse output each time an input appears at any one of its inputs, d. a sawtooth generator to receive said synchronizing pulse output from said OR gate and to produce a linear varying output voltage that is returned to its starting level with each said synchronizing pulse at its input, e. a differential comparator and analog to digital converter combination to receive said varying output from said sawtooth generator and to combine same with the differential sum of a reference input and and a control feedback input to produce a variable width pulse output, Said control feedback signal derived by sensing the output developed by the polyphase digital controller, f. a clock generator to produce pulses at a constant rate, g. an AND gate to receive the pulse output from said clock generator and the output signal of said differential comparator and analog to digital converter combination to produce output pulses of a varying number which is a function of the sum of said inputs to said AND gate, h. a frequency divider to provide a frequency division of its input derived from said clock''s output, i. a 12 bit up counter to receive the pulse from said AND gate and the OR gate output to provide a binary coded output of the sum of the number of pulses appearing at its inputs, j. a 12 bit down counter, set gate and signal gate for each of said polyphases, said set gate of each 12 bit down counter receiving said binary coded output which is distributed to each phase controlled and which provides one input for each of said set gates where each down counter has its counting cycle and the transfer of said binary coded information is initiated by a pulse output from the zero crossing detector associated with that phase, which provides a second input to said set gate and an input to said signal gate, said signal gate''s opening permits the said down counter to count the output pulses from said frequency divider which provides a second input to said signal gates, said frequency divider provides a frequency division of its input derived from the output of said clock, equal to the number of phases of the power input, each of said signal gates whose output provides the input to each of said down counters in turn providing a pulse output when the interval count reaches zero, said each down counter''s pulse outputs provide a third input to said respective signal gates, k. SCR pre-amplifiers to receive the pulse output from said 12 bit down counters, said SCR pre-amplifiers perform the function of raising their respective inputs to a value level sufficient to fire the SCR to start conduction which continues until the associated phase reverses polarity, said SCR remaining nonconducting for a time which is proportional to the differential between the reference and the control feedback, all phase control elements being supplied with binary control data from the same source, thus balance''s maintained between all phases.