Collector-up semiconductor circuit structure for binary logic

Claim 1

In a collector-up binary circuit structure of the type utilizing vertical active devices the structure comprising, a semiconductor body of one conductivity type having a planar surface, spaced first, second, third and fourth vertical transistors formed in said body including opposite conductivity base regions formed in said body extending to said surface, and one conductivity collector regions formed in the respective base regions extending to said surface, said body forming the emitter region for said transistors, fifth, sixth, seventh and eighth vertical transistors, and fifth and sixth transistors formed in the base region of said second transistor including spaced one conductivity regions formed in said base region and extending to said surface, said second transistor base region forming the collectors of said fifth and sixth transistors, said spaced one conductivity regions forming the respective base regions of said fifth and sixth transistors, and opposite conductivity regions formed in the respective base regions of said fifth and sixth transistors extending to said surface to form the emitter regions of said fifth and sixth transistors, said seventh and eighth transistors formed in the base region of said fourth transistor including spaced one conductivity regions formed in said base region and extending to said surface, said base region forming the collectors of said seventh and eighth transistors, said spaced one conductivity regions forming the base regions of said seventh and eighth transistors, and opposite conductivity regions formed in the respective base regions of said seventh and eighth transistors and extending to said surface to form the emitter regions of said seventh and eighth transistors and interconnecting means for connecting said structure as a binary circuit having first and second voltage supply terminals, said interconnecting means including means for connecting the base regions of said fifth and seventh transistors to a binary input, connecting the base regions of said sixth and eighth transistors to the complement of said binary input, connecting the collector region of the said third transistor to the emitter regions of said sixth and eighth transistors, connecting the collector region of said fourth transistor to the base region of said third transistor, connecting the base regions of said first and third transistors and the collector regions of said fifth, sixth, seventh and eighth regions to the first terminal of a voltage supply and the semiconductor body to the second terminal of a voltage supply, connecting the collector of said seventh transistor, the collector of said second transistor and the base of said first transistor to the binary output terminal, connecting the collector of said fifth transistor and the collector of said first transistor to the binary complement output terminal, so that a binary circuit is provided.