Apparatus and method for regenerating charge

Claim 2

A semiconductor apparatus including first and second charge transfer device sections of the type adapted for the storage and serial transfer of charge carriers localized in induced potential wells along a surface portion of a body by sequentially applying a plurality of differing potentials to successive portions of the surface and further adapted for logical bit regeneration, said apparatus comprising: means for detecting a charge packet output of the first charge transfer device section and for multiplying said charge packet by a multiplication factor so that after multiplication the difference in the amount of charge in a charge packet representing a logical 1 and in a charge packet representing a logical 0 is at least as great as the maximum charge storage capacity of a potential well of the second charge transfer device section, said means for multiplying including a semiconductor charge storage region controlled by an overlying electrode of such geometry as to produce a sufficient storage capacitance that the region in response to said output stores a charge packet which is amplified compared with the storage packet output; means for subtracting a fixed quantity of charge from the multiplied charge packet, sufficient to remove the charge of a charge packet representing a logical zero, said means for subtracting including a second semiconductor charge storage region controlled by an overlying electrode; and means including a localized impurity zone charge sink for limiting the amount of charge in the charge packet to a maximum value equal to the minimum charge storage capacity of a potential well of the second charge transfer device section.

Claim 3

Apparatus as recited in claim 1 wherein the means for multiplying includes: means for detecting the charge carriers in the charge packet, means for producing a potential level proportional to the number of charge carriers in the charge packet, means for providing a source of charge carriers, means for providing a charge storage region with a charge storage capacity at least as great as the charge packet, means for providing a charge flow path between the charge source and the charge storage region, means for inducing a potential barrier proportional to the potential level in the charge flow path between the charge source and the charge storage region, and means for filling the charge storage region to a potential level equal to the potential barrier.

Claim 4

Apparatus as recited in claim 2 wherein the means for filling the charge storage region includes: means for applying a potential level greater than the potential barrier to the source of charge carriers, means for filling the charge storage region to the potential level applied to the source of charge carriers, means for reducing the potential level applied to the source of charge carriers to below the level of the potential barrier, and means for reducing the potential level of the charge carriers in the charge storage region to the potential level of the potential barrier.

Claim 5

Apparatus as recited in claim 1 wherein the means for subtracting includes: means for filling a charge storage region having a charge storage capacity equal to the amount to be subtracted with charge from the multiplied charge packet, and means for retaining the remainder of the multiplied charge packet.

Claim 6

Apparatus as recited in claim 1 wherein the means for limiting includes: means for filling a charge storage region having a charge storage capacity equal to the minimum charge storage capacity of a potential well of the charge storage device with charge carriers from the charge packet, means for removing the remaining charge carriers in the charge packet, and means for retaining the charge carriers stored in the charge storage region.

Claim 7

Apparatus as recited in claim 1 further comprising: means for providing a charge packet equal in size to that representing a logical one, means for splitting the charge packet into parts whereby one of the parts is a small amount of charge relative to the amount of charge representing a logical 1, and means for adding the small amount of charge to the charge packet to be regenerated after subtraction of the fixed quantity of charge.

Claim 8

A semiconductor apparatus of the type adapted for the storage and serial transfer of charge carriers localized in induced potential wells along a surface portion of a body of a first type semiconductivity by sequentially applying a plurality of differing potentials to successive portions of the surface through field plate electrodes and further adapted for logical bit regeneration, said apparatus comprising: a first zone of a second type semiconductivity disposed within the body and adjacent one of the field plate electrodes for sensing the number of charge carriers existing under said one field plate electrode, a second zone of the second type semiconductivity disposed within the body, a source electrode contacting the second zone for supplying charge carriers, an output electrode for accumulating charge carriers and creating an output potential well, and a control field plate electrode in contact with the first zone, disposed over and insulated from the body, and between the source electrode and the output electrode for creating in the body beneath the control field plate electrode a control potential barrier, the apparatus further including: an amplifying field plate electrode disposed over and insulated from the body and between the control field plate electrode and the output electrode, for creating in the body beneath the amplifying field plate electrode an amplifying potential well with a charge storage capacity greater than the charge storage capacity of the first zone, a third zone of the second type semiconductivity disposed within the body, a first sink field plate electrode contacting the third zone for accumulating charge carriers, a transfer field plate electrode disposed over and insulated from the body, and between the amplifying field plate electrode and the output electrode and between the amplifying field plate electrode and the first sink field plate electrode, for creating in the body beneath the transfer field plate electrode a transfer potential well with a charge storage capacity at least as great as the charge storage capacity of the amplifying potential well, a subtraction field plate electrode disposed over and insulated from the body, and between the transfer field plate electrode and the first sink field plate electrode, for creating in the body beneath the subtraction field plate electrode a subtraction potential well with a charge storage capacity less than the charge storage capacity of the amplifying potential well, a fourth zone of the second type semiconductivity disposed within the body, a second sink field plate electrode contacting the fourth zone for accumulating charge carriers, and a limiting field plate electrode disposed over and insulated from the body and between the transfer field plate electrode and the output electrode and between the transfer field plate electrode and the second sink field plate electrode, for creating in the body beneath the limiting field plate electrode a limiting potential well with a charge storage capacity not greater than the charge storage capacity of the output potential well.

Claim 9

A semiconductor apparatus of the type adapted for the storage and serial transfer of charge carriers localized in induced potential wells along a surface portion of a body of a first type semiconductivity by sequentially applying a plurality of differing potentials to successive portions of the surface through field plate electrodes and further adapted for logical bit regeneration, said apparatus comprising: a first zone of a second type semiconductivity disposed within the body and adjacent one of the field plate electrodes for sensing the number of charge carriers existing under said one field plate electrode, a second zone of the second type semiconductivity disposed within the body, a source electrode contacting the second zone for supplying charge carriers, an output electrode for accumulating charge carriers and creating an output potential well, and a control field plate electrode in contact with the first zone, disposed over and insulated from the body, and between the source electrode and the output electrode for creating in the body beneath the control field plate electrode a control potential barrier, the apparatus further including: an amplifying field plate electrode disposed over and insulated from the body and between the control field plate electrode and the output electrode, for creating in the body beneath the amplifying field plate electrode an amplifying potential well with a charge storage capacity greater than the charge storage capacity of the first zone, a third zone of the second type semiconductivity disposed within the body, a first sink field plate electrode contacting the third zone for accumulating charge carriers, a transfer field plate electrode disposed over and insulated from the body, and between the amplifying field plate electrode and the output electrode and between the amplifying field plate electrode and the first sink field plate electrode, for creating in the body beneath the transfer field plate electrode a transfer potential well with a charge storage capacity at least as great as the charge storage capacity of the amplifying potential well, a subtraction field plate electrode disposed over and insulated from the body, and between the transfer field plate electrode and the first sink field plate electrode, for creating in the body beneath the subtraction field plate electrode a subtraction potential well with a charge storage capacity less than the charge storage capacity of the amplifying potential well, a fourth zone of the second type semiconductivity disposed within the body, a second sink field plate electrode contacting the fourth zone for accumulating charge carriers, and a limiting field plate electrode disposed over and insulated from the body and between the transfer field plate electrode and the output electrode and between the transfer field plate electrode and the second sink field plate electrode, for creating in the body beneath the limiting field plate electrode a limiting potential well with a charge storage capacity not greater than the charge storage capacity of the output potential well.

Claim 10

Apparatus as recited in claim 7 in combination with means for applying to the source electrode a potential level of greater magnitude and shorter duration than the magnitude and duration of any potential level of the control potential barrier.

Claim 11

Apparatus as recited in claim 7 in combination with means for maintaining a DC bias potential on the amplifying field plate electrode.

Claim 12

A semiconductor apparatus as recited in claim 7 further comprising: a blocking electrode disposed over and insulated from the body, and between the control electrode and the amplifying electrode for creating in the body beneath the blocking electrode a potential barrier.

Claim 13

A semiconductor apparatus as recited in claim 7 further comprising: a diverting field plate electrode disposed over and insulated from the body, and between the transfer field plate electrode and the limiting electrode for creating in the body beneath the diverting field plate electrode a potential barrier.

Claim 14

Apparatus as recited in claim 11 in combination with means for applying to the blocking electrode a potential level of greater magnitude and shorter duration than the magnitude and duration of any potential level applied to the transfer electrode.

Claim 15

A semiconductor apparatus as recited in claim 7 further comprising an intermediate field plate electrode disposed over and insulated from the body, and between the subtraction field plate electrode and the first sink field plate electrode creating in the body beneath the intermediate field plate electrode a potential barrier.

Claim 16

A semiconductor apparatus as recited in claim 13 wherein the intermediate field plate electrode and the first sink field plate electrode are conductively connected.

Claim 17

A semiconductor apparatus as recited in claim 7 further including means for generating a charge packet representing a logical zero comprising: a fifth zone of the second type semiconductivity disposed within the body and spaced from the limiting electrode, a second source electrode contacting the fifth zone for supplying charge carriers, a second transfer field plate electrode disposed over and insulated from the body, and between the second source electrode and the limiting electrode for creating in the body beneath the second transfer field plate electrode a second transfer potential well with a charge storage capacity not greater than the charge storage capacity of the output potential well, a storage field plate electrode disposed over and insulated from the body, and between the second transfer electrode and the limiting electrode for creating in the body beneath the storage field plate electrode a storage potential well, a dividing field plate electrode disposed over and insulated from the body, and between the storage field plate electrode and the limiting electrode for creating in the body beneath the dividing field plate electrode a potential barrier, a fat zero electrode disposed over and insulated from the body, and between the dividing field plate electrode and the limiting electrode for creating in the body beneath the fat zero electrode a fat zero potential well, with a charge storage capacity greater than zero, a sixth impurity zone of the second type semiconductivity disposed within the body and spaced from the storage field plate electrode, a third sink field plate electrode contacting the sixth zone for accumulating charge carriers, and a barrier field plate electrode disposed over and insulated from the body, and between the third sink field plate and the storage field plate electrode for creating in the body beneath the barrier field plate electrode a potential barrier to control the flow of charge carriers from the storage potential well to the sixth zone.

Claim 18

A semiconductor apparatus as recited in claim 15 wherein: the barrier field plate electrode and the third sink field plate electrode are conductively connected.

Claim 19

A semiconductor apparatus as recited in claim 15 wherein: the ratio of the charge storage capacity of the fat zero potential well to the charge storage capacity of the storage potential well is the same as the ratio of the amount of charge in a logical zero to the amount of charge difference between a logical one and a logical zero.

Claim 20

Apparatus as recited in claim 15 in combination with means for applying to the dividing field plate electrode a potential level greater in magnitude and shorter in duration than the magnitude and duration of any potential level applied either to the storage field plate electrode or to the fat zero electrode.

Claim 23

A method of regenerating charge as recited in claim 19 further comprising adding to a charge packet representing a logical 0 a small amount of charge relative to the amount of charge representing a logical 1.

Claim 24

A method as recited in claim 20 wherein the charge is added by the steps of: providing a charge packet equal in size to that representing a logical 1, splitting the charge packet into parts whereby one of the parts is the magnitude of the desired charge addition to a logical 0, and adding the part equal to the magnitude of the desired charge addition to the charge packet to be regenerated after subtraction of the fixed quantity of charge.

Claim 25

A method as recited in claim 19 wherein multiplying the charge packet comprises the steps of: detecting the charge carriers in the charge packet, producing a potential level proportional to the number of charge carriers in the charge packet, providing a source of charge carriers, providing a charge storage region with a charge storage capacity at least as great as the charge packet, providing a charge flow path between the charge source and the charge storage region, inducing a potential barrier proportional to the potential level in the charge flow path between the charge source and the charge storage region, and filling the charge storage region to a potential level equal to the potential barrier.

Claim 26

A method as recited in claim 22 wherein filling the charge storage region to a potential level equal to the potential barrier comprises the steps of: applying a potential level greater than the potential barrier to the source of charge carriers, filling the charge storage region to the potential level applied to the source of charge carriers, reducing the potential level applied to the source of charge carriers to below the level of the potential barrier, and reducing the potential level of the charge carriers in the charge storage region to the potential level of the potential barrier.

Claim 27

A method as recited in claim 19 wherein subtracting a fixed quantity of charge from the multiplied charge packet comprises the steps of: filling a charge storage region having a charge storage capacity equal to the amount to be subtracted with charge from the multiplied charge packet, and retaining the remainder of the multiplied charge packet.

Claim 28

A method as recited in claim 19 wherein limiting the amount of charge in the packet comprises the steps of: filling a charge storage region having a charge storage capacity equal to the minimum charge storage capacity of a potential well of the charge storage device with charge carriers from the charge packet, removing the remaining charge carriers in the charge packet, and retaining the charge carriers stored in the charge storage region.