Patent US3936929A successfully refreshed from Google Patents.
US3936929A
Expired / Lapsed
US
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Fet and bipolar device and circuit process with maximum junction control
Assignee: Texas Instruments Inc
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Filing: 1974-06-26
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Granted: 1976-02-10
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Expires: 1994-06-26
Abstract
Abstract Disclosed are improved field-effect and bipolar semiconductor devices and the method of making them, wherein maximum junction control provides highly predictable device parameters. Low temperature epitaxial depositions provide tight junction thickness and resistivity control, and an orientation dependent etch forms grooves circumscribing portions of the host substrate and overlying epitaxial layers to provide dielectrically isolated single crystalline mesas utilized in forming electronic devices. This is a division of application Ser. No. 275,116, filed July 26, 1972.
Inventors
- 👤 Kenneth E. Bean
- 👤 William W. Lloyd
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 14:13
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/40; H10D84/401; H10D84/01; H10D84/0107; H10D84/0109; H10D84/02; H10D84/03; H10D84/038; H10D99/00; H10P; H10P90/00; H10P90/19; H10P90/1904; H10P90/1906; H10W; H10W10/00; H10W10/01; H10W10/021; H10W10/061; H10W10/10; H10W10/181; H10W10/20; Y; Y10; Y10S; Y10S148/00; Y10S148/051; Y10S148/053; Y10S148/085; Y10S148/102; Y10S148/145
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
182 words
A method for producing dielectrically isolated electronic devices on a supporting electrically isolated substrate comprising the steps of: a. forming a plurality of orientation-dependent-etched grooves of precisely-known, different depths in a low-resistivity monocrystalline semiconductor body of one conductivity type, b. forming an insulation layer on said body and in said grooves, c. depositing a polycrystalline semiconductor support layer on said insulation layer, d. removing monocrystalline semiconductor material from the backside of said body, until a first layer having the desired thickness is achieved, as indicated by exposure of said insulation layer in the bottom of a selective groove, e. forming a second monocrystalline semiconductor layer of the other conductivity type overlying said first layer, to a desired thickness as indicated by said grooves, f. forming isolation moats circumscribing said first and second layers at a location spaced from said grooves, said moats extending to said substrate and providing a single crystalline mesa comprising said first and second layers, and g. forming semiconductor pockets of said other conductivity type selectively spaced within the surface of said second layer to provide active device regions.
Claim 2
Independent Claim
182 words
A method for producing dielectrically isolated electronic devices on a supporting electrically isolated substrate comprising the steps of: a. forming a plurality of orientation-dependent-etched grooves of precisely-known, different depths in a low-resistivity monocrystalline semiconductor body of one conductivity type, b. forming an insulation layer on said body and in said grooves, c. depositing a polycrystalline semiconductor support layer on said insulation layer, d. removing monocrystalline semiconductor material from the backside of said body, until a first layer having the desired thickness is achieved, as indicated by exposure of said insulation layer in the bottom of a selective groove, e. forming a second monocrystalline semiconductor layer of the other conductivity type overlying said first layer, to a desired thickness as indicated by said grooves, f. forming isolation moats circumscribing said first and second layers at a location spaced from said grooves, said moats extending to said substrate and providing a single crystalline mesa comprising said first and second layers, and g. forming semiconductor pockets of said other conductivity type selectively spaced within the surface of said second layer to provide active device regions.
Claim 3
Dependent Claim
18 words
The method of claim 1 wherein said substrate and said first and second layers are (100) oriented silicon.
Claim 4
Dependent Claim
34 words
The method of claim 1 and including the step of selectively forming a region of said one conductivity type in and through said second layer providing a means for electrically contacting said first layer.
Claim 5
Dependent Claim
39 words
The method of claim 3 and prior to the step of forming a first layer, the step of selectively removing any damaged regions from the upper surface of said substrate to provide a damage free surface on said substrate.
Claim 6
Dependent Claim
25 words
The method of claim 1 wherein said pockets are of said one conductivity type and form source and drain regions to provide a field-effect transistor.
Claim 7
Dependent Claim
26 words
The method of claim 1 wherein said pockets are of said one conductivity type and form collector and emitter regions to provide a lateral bipolar transistor.
Claim 8
Dependent Claim
23 words
The method of claim 1 wherein said pockets are of said one conductivity type to provide emitter regions to thereby provide a transistor.
Claim 9
Dependent Claim
22 words
The method for producing dielectrically isolated electronic devices according to claim 1 wherein said step of forming isolation moats provides air isolation.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-02-09 | 1979-08-11 | 1980-02-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-02-09 | 1983-08-11 | 1984-02-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-02-09 | 1987-08-11 | 1988-02-10 | $7700.00 | Window Closed / Lapsed |