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US3936759A
Expired / Lapsed
US
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Offset reduction apparatus for analog circuits
Assignee: United States Department of the Air Force
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Filing: 1974-04-17
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Granted: 1976-02-03
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Expires: 1994-04-17
Abstract
Abstract An offset reduction apparatus for an analog circuit in which the analog signal input to the loop is forced to zero and the loop output is determined. The previously determined value of the offsets is subtracted from the total output, thus leaving only the desired signal.
Inventors
- 👤 Gary W. Macheel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 16:24
CPC Classifications
H; H03; H03F; H03F1/00; H03F1/30; H03F1/303; H03M; H03M1/00; H03M1/12; H03M1/64; H03M1/645
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
168 words
An offset reduction apparatus for analog circuits comprising in combination: means for forcing the input of an analog circuit to zero, the output of said analog circuit being the DC offset of said analog circuit, said analog circuit receiving input signals, said analog circuit having a negative input terminal, said analog circuit providing an error signal in response to said input signals, said error signal being an output signal and said DC offset, and means for storing and subtracting said DC offset connected to said output of said analog circuit, said storing and substracting means storing said DC offset from said analog circuit, said storing and substracting means substracting said DC offset from said error signal, a compensation network connected between said negative input terminal and ground, said compensation network providing a constant DC output from said analog circuit during normal and correction circuit operation, said compensation network comprising a pair of resistors connected in series and a switch connected from the junction of said resistors to ground.
Claim 2
Dependent Claim
168 words
An offset reduction apparatus for analog circuits comprising in combination: means for forcing the input of an analog circuit to zero, the output of said analog circuit being the DC offset of said analog circuit, said analog circuit receiving input signals, said analog circuit having a negative input terminal, said analog circuit providing an error signal in response to said input signals, said error signal being an output signal and said DC offset, and means for storing and subtracting said DC offset connected to said output of said analog circuit, said storing and substracting means storing said DC offset from said analog circuit, said storing and substracting means substracting said DC offset from said error signal, a compensation network connected between said negative input terminal and ground, said compensation network providing a constant DC output from said analog circuit during normal and correction circuit operation, said compensation network comprising a pair of resistors connected in series and a switch connected from the junction of said resistors to ground.
Claim 3
Dependent Claim
50 words
An offset reduction apparatus as described in claim 1 wherein said forcing means comprises a switch circuit connected between said analog circuit input and ground, said switch circuit being open during normal analog circuit operation, said switch circuit being switched to ground to force said analog circuit input to zero.
Claim 4
Dependent Claim
85 words
An offset reduction apparatus as described in claim 1 wherein said means for storing and subtracting comprises a resistor and a capacitor in series, said output of said analog circuit being connected to said resistor, said capacitor receiving said DC offset from said analog circuit through said resistor, and a switch connected from said capacitor to ground, said capacitor storing said DC offset when said switch is closed to ground, said capacitor substracting said DC offset from said error signal when said switch is opened.
Claim 5
Dependent Claim
68 words
An offset reduction apparatus as described in claim 1 wherein further including input impedance means to maximize input impedance and minimize bias currents, said input impedance means being connected to said storing and substracting means, said input impedance means having a bias current flow through said storing and substrating means, said bias current flow having a negligible effect upon the current flow in said storing means during operation.
Claim 6
Dependent Claim
52 words
An offset reduction apparatus as described in claim 4 wherein said input impedance means comprises an operational amplifier having a first and second input terminal and an output terminal, said first input terminal being connected to said storing and subtracting means, said second input terminal being directly connected to said output terminal.
Claim 7
Dependent Claim
17 words
An offset reduction apparatus as described in claim 5 further including filter means to provide noise rejection.
Claim 8
Dependent Claim
24 words
An offset reduction apparatus as described in claim 6 further including a level detector to clearly define said output signal from said analog circuit.
Claim 9
Dependent Claim
40 words
An offset reduction apparatus as described in claim 7 wherein said level detector comprises an operational amplifier with a first and second input terminal, said first input terminal receives said output signal, said second input terminal being connected to ground.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-02-02 | 1979-08-04 | 1980-02-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-02-02 | 1983-08-04 | 1984-02-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-02-02 | 1987-08-04 | 1988-02-03 | $7700.00 | Window Closed / Lapsed |