Integrating network using at least one d-c amplifier

Claim 2

An integrating network comprising: an integrator having an output and having an input for receiving an input voltage signal, and being formed by a first d-c amplifier and time-constant means connected to said first d-c amplifier, drift memory circuit means connected between the output and input of the integrator for feeding back in the opposite polarity the output of the first d-c amplifier to the input of the integrator in the absence of an input voltage at an input of the first d-c amplifier so as to obtain a stationary condition and for continuously sending out, as a feedback signal, a voltage fed back to the input of the integrator at the stationary condition, the feedback signal having a value substantially equal to the drift voltage of the first d-c amplifier converted in terms of the input of the integrator, whereby an input voltage signal is integrated in the integrator without error caused by the drift of the first d-c amplifier, level detector means connected to the output of the integrator to produce a first control pulse when the output of the integrator exceeds a predetermined reference level and to produce a second control pulse when the output of the integrator crosses the predetermined reference level in the decreasing direction, a time measuring means coupled to the level detector for generating a third control pulse in response to the termination of a predetermined first time period measured from the first control pulse and for measuring a second time period between the third control pulse and the second control pulse, a reference d-c source, and input switch means connected to said reference d-c source and to the input of the integrator for applying the input voltage signal to the integrator in response to the first control pulse, for applying a reference d-c voltage from the d-c source to the integrator in response to the third control pulse, and for shorting the input of the integrator in response to the second control pulse, whereby the level of the input voltage signal can be determined by the ratio of the second time period to the first time period, multiplied by the value of the reference voltage from the reference d-c source.

Claim 3

An integrating netwOrk according to claim 1, in which the drift memory circuit means comprises a second d-c amplifier, a switch connected to the output of the second d-c amplifier, means for actuating said switch to a closed state in the absence of said input voltage at the input of the first d-c amplifier and for actuating said switch to an open state upon application of the input voltage to the first d-c amplifier, and a capacitor connected in series between the switch and ground.

Claim 4

An integrating network according to claim 1, in which the drift memory circuit means comprises a switch, and means for actuating said switch to a switched-on state in the absence of said input voltage at the first d-c amplifier, and to a switched-off state at the application of the input voltage to the d-c first amplifier, a capacitor connected between the switch and ground, and a second d-c amplifier connected to the junction between the switch and the capacitor.

Claim 5

An integrating network according to claim 1, in which the first d-c amplifier is a differential amplifier having a first input terminal receiving the input voltage signal to be integrated and a second input terminal receiving the feedback signal.

Claim 6

An integrating network, comprising: an integrator having an input and an output, and being formed by a first d-c amplifier and time-constant means connected to said first d-c amplifier, a second d-c amplifier having an output connected to said input of the integrator, and having an input for the application of an input voltage signal thereto, drift memory circuit means connected between the output and input of the integrator for feeding back in the opposite polarity the output of the first d-c amplifier to the input of the integrator in the absence of said input voltage at an input of the second d-c amplifier so as to establish a quiescent condition and for continuously sending out, as a feedback signal, a voltage fed back to the input of the integrator at the quiescent condition, the feedback signal having a value substantially equal to the drift voltages of the first and second d-c amplifiers converted in terms of the input of the integrator, whereby said input voltage signal applied through the second d-c amplifier is integrated without error caused by the drift of the first and second d-c amplifiers.

Claim 7

An integrating network, comprising: an integrator having an input and an output, and being formed by a first d-c amplifier and time-constant means connected to said first d-c amplifier, a second d-c amplifier having an output connected to said input of the integrator, and having an input for the application of an input voltage signal thereto, drift memory circuit means connected between the output and input of the integrator for feeding back in the opposite polarity the output of the first d-c amplifier to the input of the integrator in the absence of said input voltage at an input of the second d-c amplifier so as to establish a quiescent condition and for continuously sending out, as a feedback signal, a voltage fed back to the input of the integrator at the quiescent condition, the feedback signal having a value substantially equal to the drift voltages of the first and second d-c amplifiers converted in terms of the input of the integrator, whereby said input voltage signal applied through the second d-c amplifier is integrated without error caused by the drift of the first and second d-c amplifiers.

Claim 8

An integrating network according to claim 5, in which the drift memory circuit means comprises a third d-c amplifier, a switch connected to the output of the third d-c amplifier, means for actuating said switch to a closed state in the absence of said input voltage at the input of the first d-c amplifier and for actuating said switch to an open state upon application of the input voltage to the first d-c amplifier, and a capacitor connected in series between the switch and ground.

Claim 9

An integrating network according to claim 5, in which the drift memory circuit means comprises a switch, and means for actuating said switch to a switch-on state in the absence of said input voltage at the first d-c amplifier, and to a switched-off state at the application of the input voltage to the d-c first amplifier, a capacitor connected between the switch and ground, and a third d-c amplifier connected to the junction between the switch and the capacitor.

Claim 10

An integrating network according to claim 5, in which the first d-c amplifier is a differential amplifier having a first input terminal receiving the input voltage signal to be integrated and a second input terminal receiving the feedback signal.

Claim 11

An integrating network, comprising: an integrator having an input and an output, and being formed by a first d-c amplifier and time-constant means connected to said first d-c amplifier, a second d-c amplifier having an output connected to said input of the integrator, and drift memory circuit means connected between the output and input of the integrator for feeding back in the opposite polarity the output of the first d-c amplifier to the iNput of the integrator in the absence of an input voltage at an input of the second d-c amplifier so as to obtain a stationary condition and for continuously sending out, as a feedback signal, a voltage fed back to the input of the integrator at the stationary condition, the feedback signal having a value substantially equal to the drift voltages of the first and second d-c amplifiers converted in terms of the input of the integrator, whereby an input voltage signal applied through the second d-c amplifier is integrated without error caused by the drift of the first and second d-c amplifiers, level detector means connected to the output of the integrator to produce a first control pulse when the output of the integrator exceeds a predetermined reference level and to produce a second control pulse when the output of the integrator crosses the predetermined reference level in the decreasing direction, a time measuring means coupled to the level detector for generating a third control pulse in response to the termination of a predetermined first time period measured from the first control pulse and for measuring a second time period between the third control pulse and the second control pulse, a reference d-c source, and input switch means connected to said reference d-c source and to the input of the second d-c amplifier for applying the input voltage signal to the second d-c amplifier in response to the first control pulse, for applying a reference d-c voltage from the d-c source to the second d-c amplifier in response to the third control pulse, and for shorting the input of the second d-c amplifier in response to the second control pulse, whereby the level of the input voltage signal can be determined by the ratio of the second time period to the first time period, multiplied by the value of the reference voltage of the d-c source.

Claim 12

An integrating network, comprising: an integrator having an input and an output, and being formed by a first d-c amplifier and time-constant means connected to said first d-c amplifier, a second d-c amplifier having an output connected to said input of the integrator, and drift memory circuit means connected between the output and input of the integrator for feeding back in the opposite polarity the output of the first d-c amplifier to the iNput of the integrator in the absence of an input voltage at an input of the second d-c amplifier so as to obtain a stationary condition and for continuously sending out, as a feedback signal, a voltage fed back to the input of the integrator at the stationary condition, the feedback signal having a value substantially equal to the drift voltages of the first and second d-c amplifiers converted in terms of the input of the integrator, whereby an input voltage signal applied through the second d-c amplifier is integrated without error caused by the drift of the first and second d-c amplifiers, level detector means connected to the output of the integrator to produce a first control pulse when the output of the integrator exceeds a predetermined reference level and to produce a second control pulse when the output of the integrator crosses the predetermined reference level in the decreasing direction, a time measuring means coupled to the level detector for generating a third control pulse in response to the termination of a predetermined first time period measured from the first control pulse and for measuring a second time period between the third control pulse and the second control pulse, a reference d-c source, and input switch means connected to said reference d-c source and to the input of the second d-c amplifier for applying the input voltage signal to the second d-c amplifier in response to the first control pulse, for applying a reference d-c voltage from the d-c source to the second d-c amplifier in response to the third control pulse, and for shorting the input of the second d-c amplifier in response to the second control pulse, whereby the level of the input voltage signal can be determined by the ratio of the second time period to the first time period, multiplied by the value of the reference voltage of the d-c source.

Claim 13

An integrating network, comprising: an integrator having an input and an output, and being formed by a first d-c amplifier and time-constant means connected to said first d-c amplifier, a second d-c amplifier having an input connected to said output of the integrator, and drift memory circuit means connected between the output of the second amplifier and the input of the integrator for feeding back in the opposite polarity the output of the second d-c amplifier to the input of the integrator in the absence of an input voltage at the input of the first d-c amplifier so as to obtain a stationary condition and for continuously sending out, as a feedback signal, a voltage fed back to the input of the integrator at the stationary condition, the fed back signal having a value substantially equal to the drift voltages of the first and second d-c amplifiers converted in terms of the input of the integrator, whereby an input voltage is integrated in the integrator without error caused by the drift of the first and second d-c amplifiers so as to produce an integrated output of the input voltage at the output of the second amplifier, level detector means connected to the output of the second d-c amplifier to produce a first control pulse when the output of the second d-c amplifier exceeds a predetermined reference level and to produce a second control pulse when the output of the second d-c amplifier crosses the predetermined reference level in the decreasing direction, a time measuring means coupled to the level detector for generating a third control pulse in response to the termination of a predetermined first time period measured from the first control pulse and for measuring a second time period between the third control pulse and the second control pulse, a reference d-c source, and input switch means connected to said reference d-c source and to the input of the integrator for applying the input voltage signal to the integrator in response to the first control pulse, for applying a reference d-c voltage from the d-c source to the integrator in response to the third control pUlse, and for shorting the input of the integrator in response to the second control pulse, whereby the level of the input voltage signal can be determined by the ratio of the second time period to the first time period, multiplied by the value of the reference voltage from the reference d-c source.

Claim 14

An integrating network, comprising: an integrator having an input and an output, and being formed by a first d-c amplifier and time-constant means connected to said first d-c amplifier, a second d-c amplifier having an input connected to said output of the integrator, and drift memory circuit means connected between the output of the second amplifier and the input of the integrator for feeding back in the opposite polarity the output of the second d-c amplifier to the input of the integrator in the absence of an input voltage at the input of the first d-c amplifier so as to obtain a stationary condition and for continuously sending out, as a feedback signal, a voltage fed back to the input of the integrator at the stationary condition, the fed back signal having a value substantially equal to the drift voltages of the first and second d-c amplifiers converted in terms of the input of the integrator, whereby an input voltage is integrated in the integrator without error caused by the drift of the first and second d-c amplifiers so as to produce an integrated output of the input voltage at the output of the second amplifier, level detector means connected to the output of the second d-c amplifier to produce a first control pulse when the output of the second d-c amplifier exceeds a predetermined reference level and to produce a second control pulse when the output of the second d-c amplifier crosses the predetermined reference level in the decreasing direction, a time measuring means coupled to the level detector for generating a third control pulse in response to the termination of a predetermined first time period measured from the first control pulse and for measuring a second time period between the third control pulse and the second control pulse, a reference d-c source, and input switch means connected to said reference d-c source and to the input of the integrator for applying the input voltage signal to the integrator in response to the first control pulse, for applying a reference d-c voltage from the d-c source to the integrator in response to the third control pUlse, and for shorting the input of the integrator in response to the second control pulse, whereby the level of the input voltage signal can be determined by the ratio of the second time period to the first time period, multiplied by the value of the reference voltage from the reference d-c source.

Claim 15

An integrating network, comprising: an integrator having an input and an output, and being formed by a first d-c amplifier and time-constant means connected to the first d-c amplifier, a second d-c amplifier having an output connected to said input of the integrator, a third d-c amplifier having an input connected to the output of the integrator, and drift memory circuit means connected between the output of the third amplifier and the input of the integrator for feeding back in the opposite polarity the output of the third d-c amplifier to the input of the integrator in the absence of an input voltage at the input of the second d-c amplifier so as to obtain a stationary condition and for continuously sending out, as a feedback signal, a voltage fed back to the input of the integrator at the stationary condition, the fed back signal having a value substantially equal to the drift voltages of the first, second and third d-c amplifiers converted in terms of the input of the integrator, whereby an input voltage signal applied through the second d-c amplifier is integrated in the integrator without error caused by the drift of the first, second and third d-c amplifiers so as to produce an integrated output of the input voltage at the output of the third amplifier, level detector means connected to the output of the third d-c amplifer to produce a first control pulse when the output of the third d-c amplifier exceeds a predetermined reference level and to produce a second control pulse when the output of the third d-c amplifier crosses the predetermined reference level in the decreasing direction, a time measuring means coupled to the level detector for generating a third control pulse in response to the termination of a predetermined first time period measured from the first control pulse and for measuring a second time period between the third control pulse and the second control pulse, a reference d-c source, and input switch means connected to said reference d-c source and to the input of the second d-c amplifier for applying the input voltage signal to the second d-c amplifier in response to the first control pulse, for applying a reference d-c voltage from the d-c source to the second d-c amplifier in response to the third control pulse, and for shorting the input of the second d-c amplifier in response to the second control pulse, whereby the level of the input voltage signal can be determined by the ratio of the second time period to the first time period, multiplied by the value of the reference voltage from the reference d-c source.

Claim 16

An integrating network, comprising: an integrator having an input and an output, and being formed by a first d-c amplifier and time-constant means connected to the first d-c amplifier, a second d-c amplifier having an output connected to said input of the integrator, a third d-c amplifier having an input connected to the output of the integrator, and drift memory circuit means connected between the output of the third amplifier and the input of the integrator for feeding back in the opposite polarity the output of the third d-c amplifier to the input of the integrator in the absence of an input voltage at the input of the second d-c amplifier so as to obtain a stationary condition and for continuously sending out, as a feedback signal, a voltage fed back to the input of the integrator at the stationary condition, the fed back signal having a value substantially equal to the drift voltages of the first, second and third d-c amplifiers converted in terms of the input of the integrator, whereby an input voltage signal applied through the second d-c amplifier is integrated in the integrator without error caused by the drift of the first, second and third d-c amplifiers so as to produce an integrated output of the input voltage at the output of the third amplifier, level detector means connected to the output of the third d-c amplifer to produce a first control pulse when the output of the third d-c amplifier exceeds a predetermined reference level and to produce a second control pulse when the output of the third d-c amplifier crosses the predetermined reference level in the decreasing direction, a time measuring means coupled to the level detector for generating a third control pulse in response to the termination of a predetermined first time period measured from the first control pulse and for measuring a second time period between the third control pulse and the second control pulse, a reference d-c source, and input switch means connected to said reference d-c source and to the input of the second d-c amplifier for applying the input voltage signal to the second d-c amplifier in response to the first control pulse, for applying a reference d-c voltage from the d-c source to the second d-c amplifier in response to the third control pulse, and for shorting the input of the second d-c amplifier in response to the second control pulse, whereby the level of the input voltage signal can be determined by the ratio of the second time period to the first time period, multiplied by the value of the reference voltage from the reference d-c source.

Claim 17

An integrating network, comprising: an integrator having an input and an output, and being formed by a first d-c amplifier and time-constant means connected to said first d-c amplifier, a second d-c amplifier having an input connected to said output of the integrator, and drift memory circuit means connected between the output of the second amplifier and the input of the integrator for feeding back in the opposite polarity the output of the second d-c amplifier to the input of the integrator in the absence of an input voltage at the input of the first d-c amplifier so as to obtain a stationary condition and for continuously sending out, as a feedback signal, a voltage fed back to the input of the integrator at the stationary condition, the fed back signal having a value substantially equal to the drift voltages of the first and second d-c amplifiers converted in terms of the input of the integrator, whereby an input voltage is integrated in the integrator without error caused by the drift of the first and second d-c amplifiers so as to produce an integrated oUtput of the input voltage at the output of the second amplifier.

Claim 18

An integrating network, comprising: an integrator having an input and an output, and being formed by a first d-c amplifier and time-constant means connected to said first d-c amplifier, a second d-c amplifier having an input connected to said output of the integrator, and drift memory circuit means connected between the output of the second amplifier and the input of the integrator for feeding back in the opposite polarity the output of the second d-c amplifier to the input of the integrator in the absence of an input voltage at the input of the first d-c amplifier so as to obtain a stationary condition and for continuously sending out, as a feedback signal, a voltage fed back to the input of the integrator at the stationary condition, the fed back signal having a value substantially equal to the drift voltages of the first and second d-c amplifiers converted in terms of the input of the integrator, whereby an input voltage is integrated in the integrator without error caused by the drift of the first and second d-c amplifiers so as to produce an integrated oUtput of the input voltage at the output of the second amplifier.

Claim 19

An integrating network according to claim 12, in which the drift memory circuit means comprises a third d-c amplifier, a switch connected to the output of the third d-c amplifier, means for actuating said switch to a closed state in the absence of said input voltage at the input of the first d-c amplifier and for actuating said switch to an open state upon application of the input voltage to the first d-c amplifier, and a capacitor connected in series between the switch and ground.

Claim 20

An integrating network according to claim 12, in which the drift memory circuit means comprises a switch, and means for actuating said switch to a switched-on state in the absence of said input voltage at the first d-c amplifier, and to a switched-off state at the application of the input voltage to the first d-c amplifier, a capacitor connected between the switch and ground, and a third d-c amplifier connected to the junction between the switch and the capacitor.

Claim 21

An integrating network according to claim 12, in which the first d-c amplifier is a differential amplifier having a first input terminal receiving the input voltage signal to be integrated and a second input terminal receiving the feedback signal.

Claim 22

An integrating network, comprising: an integrator having an input and an output, and being formed by a first d-c amplifier and time-constant means connected to the first d-c amplifier, a second d-c amplifier having an output connected to said input of the integrator, and having an input for the application of an input voltage signal, a third d-c amplifier having an input connected to the output of the integrator, and drift memory circuit means connected between the output of the third amplifier and the input of the integrator for feeding back in the opposite polarity the output of the third d-c amplifier to the input of the integrator in the absence of said input voltage at the input of the second d-c amplifier so as to establish a quiescent condition and for continuously sending out, as a feedback signal, a voltage fed back to the input of the integrator at the quiescent condition, the fed back signal having a value substantially equal to the drift voltages of the first, second and third d-c amplifiers converted in terms of the input of the integrator, whereby said input voltage signal applied through the second d-c amplifier is integrated in the integrator without error caused by the drift of the first, second and third d-c amplifiers so as to produce an integrated output of the input voltage at the output of the third amplifier.

Claim 23

An integrating network, comprising: an integrator having an input and an output, and being formed by a first d-c amplifier and time-constant means connected to the first d-c amplifier, a second d-c amplifier having an output connected to said input of the integrator, and having an input for the application of an input voltage signal, a third d-c amplifier having an input connected to the output of the integrator, and drift memory circuit means connected between the output of the third amplifier and the input of the integrator for feeding back in the opposite polarity the output of the third d-c amplifier to the input of the integrator in the absence of said input voltage at the input of the second d-c amplifier so as to establish a quiescent condition and for continuously sending out, as a feedback signal, a voltage fed back to the input of the integrator at the quiescent condition, the fed back signal having a value substantially equal to the drift voltages of the first, second and third d-c amplifiers converted in terms of the input of the integrator, whereby said input voltage signal applied through the second d-c amplifier is integrated in the integrator without error caused by the drift of the first, second and third d-c amplifiers so as to produce an integrated output of the input voltage at the output of the third amplifier.

Claim 24

An integrating network according to claim 16, in which the drift memory circuit means comprises a fourth d-c amplifier, a switch connected to the output of the fourth d-c amplifier, means for actuating said switch to a closed state in the absence of said input voltage at the input of the first d-c amplifier and for actuating said switch to an open state upon application of the input voltage to the first d-c amplifier, and a capacitor connected in series between the switch and ground.

Claim 25

An integrating network according to claim 16, in which the drift memory circuit means comprises a switch, and means for actuating said switch to a switched-on state in the absence of said input voltage at the first d-c amplifier, and to a switched-off state at the application of the input voltage to the d-c first amplifier, a capacitor connected between the switch and ground, and a fourth d-c amplifier connected to the junction between the switch and the capacitor.

Claim 26

An integrating network according to claim 16, in which the first d-c amplifier is a differential amplifier having a first input terminal receiving the input voltage signal to be integrated and a second input terminal receiving the feedback signal.