US3935539A
Expired / Lapsed
US
⏱️ 0.0 years remaining
A-C signal multiplying circuit by a ratio of whole numbers the numerator of which is greater than one and greater than the denominator
Assignee: United States Department of the Navy
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Filing: 1974-10-21
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Granted: 1976-01-27
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Expires: 1994-10-21
Abstract
Abstract A digital frequency correlator circuit for comparing the frequencies of a urality of a-c signals to determine if they are coherent within a predetermined number of cycles. The a-c signals are converted into digital numbers representing their frequencies. The digital numbers are subtracted and the difference is compared, utilizing an exclusive-or circuit, with a predetermined number of cycles. If the difference is greater than the predetermined number of cycles, a logic 0 is outputted. If the difference is equal to or less than the predetermined number of cycles, a logic 1 is outputted.
Inventors
- 👤 John L. Linder
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 14:53
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/22; H03K5/26; G; G01; G01R; G01R23/00; G01R23/005; G01S; G01S3/00; G01S3/02; G01S3/14; G01S3/38; G01S3/42
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
415 words
A frequency multiplier circuit for frequency-multiplying an a-c signal by a ratio of whole numbers wherein the absolute value of the numerator of said ratio is greater than the absolute value of the denominator of said ratio and greater than one comprising: a. means for providing an a-c signal; b. means for providing a clock-frequency-signal of frequency greater than said a-c signal, said clock-frequency-signal providing means having an output; c. means for receiving and dividing the frequency of said a-c signal by a first predetermined whole number greater than one said receiving and dividing means having an output; d. a differentiator circuit having an input and an output, said input being connected to said output of said means for receiving and dividing the frequency of said a-c signal by a first whole number greater than one; e. a clock gate curcuit having a clock-frequency-signal input, a second input and an output, said clock-frequency-signal input being connected to said output of said means for providing a clock-frequency-signal; f. a binary counter circuit having a first input, a second input, a first output, and a second output, said second input being connected to said output of said differentiator circuit, said first input being connected to said output of said clock gate circuit; and g. a flip-flop circuit having a first input, a second input, and an output, said first input being connected to said second output of said binary counter circuit, said second input being connected to said output of said differentiator circuit, said output of said flip-flop circuit being connected to said second input of said clock gate circuit, the signal on the output of said differentiator circuit resets said binary counter circuit and said flip-flop circuit, then said flip-flop circuit enables said clock gate circuit passing said clock frequency signal to said binary counter circuit, after counting a predetermined second whole number of cycles of said clock frequency signal, said second whole number being greater than one and greater than said first whole number, said binary counter circuit clocks said flip-flop circuit, causing said flip-flop circuit to inhibit said clock gate circuit until said differentiator circuit resets said binary counter circuit and said flip-flop circuit, whereby for every cycle of said frequency-divided a-c signal, said second whole number of cycles of said clock-frequency-signal appears on said binary counter circuit first output, said second whole number of cycles of said clock-frequency-signal appearing on said binary counter circuit first output being said ratio-of-whole-numbers, frequency multiplied, a-c signal.
Claim 2
Dependent Claim
415 words
A frequency multiplier circuit for frequency-multiplying an a-c signal by a ratio of whole numbers wherein the absolute value of the numerator of said ratio is greater than the absolute value of the denominator of said ratio and greater than one comprising: a. means for providing an a-c signal; b. means for providing a clock-frequency-signal of frequency greater than said a-c signal, said clock-frequency-signal providing means having an output; c. means for receiving and dividing the frequency of said a-c signal by a first predetermined whole number greater than one said receiving and dividing means having an output; d. a differentiator circuit having an input and an output, said input being connected to said output of said means for receiving and dividing the frequency of said a-c signal by a first whole number greater than one; e. a clock gate curcuit having a clock-frequency-signal input, a second input and an output, said clock-frequency-signal input being connected to said output of said means for providing a clock-frequency-signal; f. a binary counter circuit having a first input, a second input, a first output, and a second output, said second input being connected to said output of said differentiator circuit, said first input being connected to said output of said clock gate circuit; and g. a flip-flop circuit having a first input, a second input, and an output, said first input being connected to said second output of said binary counter circuit, said second input being connected to said output of said differentiator circuit, said output of said flip-flop circuit being connected to said second input of said clock gate circuit, the signal on the output of said differentiator circuit resets said binary counter circuit and said flip-flop circuit, then said flip-flop circuit enables said clock gate circuit passing said clock frequency signal to said binary counter circuit, after counting a predetermined second whole number of cycles of said clock frequency signal, said second whole number being greater than one and greater than said first whole number, said binary counter circuit clocks said flip-flop circuit, causing said flip-flop circuit to inhibit said clock gate circuit until said differentiator circuit resets said binary counter circuit and said flip-flop circuit, whereby for every cycle of said frequency-divided a-c signal, said second whole number of cycles of said clock-frequency-signal appears on said binary counter circuit first output, said second whole number of cycles of said clock-frequency-signal appearing on said binary counter circuit first output being said ratio-of-whole-numbers, frequency multiplied, a-c signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-01-26 | 1979-07-28 | 1980-01-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-01-26 | 1983-07-28 | 1984-01-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-01-26 | 1987-07-28 | 1988-01-27 | $7700.00 | Window Closed / Lapsed |