Inrush current limit circuit with reset response to lowered input voltage

Claim 2

An inrush current limit circuit comprising, input terminals to accept a source, output terminals to accept a load, a current limit impedance connecting at least one of said input terminals to at least one of said output terminals, a low impedance path, means to connect said low impedance path in parallel with said current limit impedance, means to operate said means to connect, current sensing means connected to sense the current in said current limit impedance, voltage monitoring means connected to monitor the voltage at said input terminals, said means to operate responsive to said current sensing means at a current below a particular low current threshold to connect said low impedance path in parallel with said current limiting impedance, said means to operate being further responsive to said voltage monitoring means at a voltage below a particular low voltage threshold to disable said means to connect and disconnect said low impedance path from a parallel connection with said current limiting impedance.

Claim 3

An inrush current limit circuit as defined in claim 1 wherein, said current sensing means comprises a first transistor whose conductivity is responsive to a bias signal generated by said current limit impedance, and said means to operate comprises a second transistor whose conductivity is responsive to said first transistor, and a relay coil responsive to the collector current of said second transistor, and said means to connect comprises a relay contact responsive to said relay coil.

Claim 4

An inrush current limit circuit as defined in claim 2 wherein, said voltage monitoring means comprises a voltage divider shunted across the input terminals, and said means to operate includes means to utilize a voltage developed by said voltage divider to bias said second transistor nonconducting.

Claim 5

In a converter circuit, means to limit the converter input current upon energization of the circuit comprising, a high impedance situated in the path of the input current, a low impedance current path shunting said high impedance and including a make and break contact, a relay coil to control said contact, and means to control the energization of said relay coil including, a first transistor situated to complete an energization path for said relay coil, a second transistor connected to be biased in response to the voltage drop across said high impedance, said second transistor connected to control the bias of said first transistor, whereby said first transistor is biased conducting to energize said relay coil and, hence, enable said low impedance path in response to a decreased current through said high impedance, and means to bias the first transistor nonconducting should said input current decrease significantly including, a voltage divider energized by a portion of the input current and connected to the control electrode of said first transistor.

Claim 6

In a converter circuit, means to limit the converter input current upon energization of the circuit comprising, a high impedance situated in the path of the input current, a low impedance current path shunting said high impedance and including a make and break contact, a relay coil to control said contact, and means to control the energization of said relay coil including, a first transistor situated to complete an energization path for said relay coil, a second transistor connected to be biased in response to the voltage drop across said high impedance, said second transistor connected to control the bias of said first transistor, whereby said first transistor is biased conducting to energize said relay coil and, hence, enable said low impedance path in response to a decreased current through said high impedance, and means to bias the first transistor nonconducting should said input current decrease significantly including, a voltage divider energized by a portion of the input current and connected to the control electrode of said first transistor.