Self-aligned transistor process

Claim 1

In the process of manufacturing semiconductor transistor devices the improvement which comprises the steps of: a. producing a uniform layer of non-conducting silicon oxide on an N-type silicon semiconductor substrate, said oxide layer having opened therein a base region window exposing a portion of said substrate surface area about 300-500 microns in diameter; b. creating a base region by introducing into said substrate through the window in said oxide layer an effective amount of impurity necessary to create P+ conductivity semiconductor characteristics; c. regenerating an integral coating of silicon oxide over the entire surface of said substrate by depositing approximately a 1000 A thick layer of silicon oxide across said base region, thereby closing said base region window; d. forming a composite oxide mask by etching through to said substrate in a single step a series of openings, each approximately 1-5 microns in diameter and 2-4 microns apart, at predetermined locations with respect to said previously created base region, said openings comprising an N+ conductivity portion and a P+ conductivity portion; e. masking a first portion of said openings and introducing into said substrate by ion implantation at temperatures below which extensive oxide growth is generated through the remaining open windows a predetermined effective amount of an impurity necessary to create N+ type conductivity regions; and thereafter f. removing the mask from said first portion of said openings and introducing through only said first portion of said windows into said substrate by ion implantation at temperatures below which extensive oxide growth is generated a predetermined effective amount of an impurity necessary to create P+ type conductivity regions.