US3925764A — Memory device

Claim 1

Independent Claim 373 words

A memory device for control pulse patterns in automatic switching control systems comprising in combination: A shift register having n + 1 register stages, where n is the number of clock pulses per pulse pattern, the input stage of said shift register having a clock input means for receiving a continuous supply of pattern clock pulses, an erase input means for receiving an erase signal and a signal input means, for receiving a working pulse pattern; a first OR circuit having its output connected to said signal input means and a first iNput connected to a source of working pulse patterns; and logic circuit means connected to said shift register for detecting the presence of a desired working pulse pattern in said register and for causing the storage thereof, said logic circuit means including a timing means responsive to an input pulse for thereafter producing an output pulse for a predetermined time period, first, second, third and fourth AND circuits, and second and third OR circuits; said first AND circuit having a first input connected to the output of said first register stage, a second input connected to the output of said second OR circuit, and its output connected to the input of said timing means; said second OR circuit having at least one input connected to the output of a register stage other than said first register stage; and second AND circuit having a first input connected to the output of said timing means, a second input connected to the output of a penultimate register stage of said shift register, and its output connected to a second input of said first OR circuit; said third AND circuit having a first input connected to the output of the last register stage of said shift register, a second input connected to said clock input means, and its output connected to one input of said third OR circuit; and said fourth AND circuit having a first input connected to the output of said timing means, a second input connected to said first input of said first OR circuit, and its output connected to a second input of said third OR circuit, the output of said third OR circuit constituting the output of said memory device.

Claim 2

Dependent Claim 373 words

A memory device for control pulse patterns in automatic switching control systems comprising in combination: A shift register having n + 1 register stages, where n is the number of clock pulses per pulse pattern, the input stage of said shift register having a clock input means for receiving a continuous supply of pattern clock pulses, an erase input means for receiving an erase signal and a signal input means, for receiving a working pulse pattern; a first OR circuit having its output connected to said signal input means and a first iNput connected to a source of working pulse patterns; and logic circuit means connected to said shift register for detecting the presence of a desired working pulse pattern in said register and for causing the storage thereof, said logic circuit means including a timing means responsive to an input pulse for thereafter producing an output pulse for a predetermined time period, first, second, third and fourth AND circuits, and second and third OR circuits; said first AND circuit having a first input connected to the output of said first register stage, a second input connected to the output of said second OR circuit, and its output connected to the input of said timing means; said second OR circuit having at least one input connected to the output of a register stage other than said first register stage; and second AND circuit having a first input connected to the output of said timing means, a second input connected to the output of a penultimate register stage of said shift register, and its output connected to a second input of said first OR circuit; said third AND circuit having a first input connected to the output of the last register stage of said shift register, a second input connected to said clock input means, and its output connected to one input of said third OR circuit; and said fourth AND circuit having a first input connected to the output of said timing means, a second input connected to said first input of said first OR circuit, and its output connected to a second input of said third OR circuit, the output of said third OR circuit constituting the output of said memory device.

Claim 3

Dependent Claim 107 words

A memory device as defined in claim 1 wherein, in dependence on the configuration of the working pulse patterns to be stored, the inputs of said second OR circuit are connected to the outputs of selected ones of said register stages so that a signal pattern typical for pulse patterns to be stored is recognized in said shift register at the earliest possible point in time within a single pulse pattern whereby said timing means releases the return line from the output of the nth register stage via said first OR circuit to said signal input means of said input register state to store the pulse pattern.

Claim 4

Dependent Claim 48 words

A memory device as defined in claim 2 wherein upon switching on of said timing means T the signal pattern to be stored is emitted at the output of said third OR circuit without delay, complete and in synchronism with the pulse pattern fed into said shift register.

Claim 5

Dependent Claim 33 words

A memory device as defined in claim 3 wherein storable and nonstorable pulse patterns are emitted after one pulse pattern length at the correct point in the pulse pattern in the stored form.

Claim 6

Dependent Claim 56 words

A memory device as defined in claim 4 wherein each working pulse pattern to be stored is a combination of a standard test pulse pattern and a basic working pulse pattern corresponding to the desired control function, so that when input contacts are switched as a result of operational requirements no test pulse will be lost.

Claim 7

Dependent Claim 49 words

A memory device as defined in claim 5 wherein only said test pulse pattern is applied to said signal input means when said working pulse pattern is not present and said test pulse pattern is passed through the memory device for the purpose of continuously monitoring said memory device.

Claim 8

Dependent Claim 74 words

A memory device as defined in claim 6 wherein when said memory device is erased by the application of an erase pulse to said erase input means to erase the shift register but said timing means has not as yet ceased producing an output signal, the test pulse fed into said memory device are switched through to the output directly via said fourth AND circuit so that the monitoring remains in effect without interruption.

Claim 9

Dependent Claim 198 words

A memory device as defined in claim 7 for an automatic switching control system of the type in which an erase signal is transmitted after each pulse pattern, wherein said logic circuit further includes fifth and sixth AND circuits and a fouRth OR circuit, said fifth AND circuit having a first innput connected to a negated output of said timing means, a second input connected to a first erase signal line on which the erase signal which is transmitted after each pulse pattern appears, and its output connected to one input of said fourth circuit, said fourth OR circuit having its other input connected to a second erase input line on which an erase pulse pattern is present when required, and its output connected to said erase input means of said first register stage of said shift register; and said sixth AND circuit having a first input connected to said negated output of said timing means, a second input connected to said output of said first register stage, a third input connected to said clock input means for receiving the continuously present clock pulse pattern and its output connected to a third input of said third OR circuit.

Claim 10

Dependent Claim 18 words

A memory device as defined in claim 8 wherein said memory device is erased after every pulse pattern.

Claim 11

Dependent Claim 69 words

A memory device as defined in claim 8 wherein upon the detection by said logic circuit means of a pulse pattern to be stored in said shift register and the switching of said timing means, the negated output of said timing means, via said fifth AND circuit blocks the erase pulses arriving on said first erase line until erase pulses on said second erase line erases said memory device.

Claim 12

Dependent Claim 172 words

A memory device as defined in claim 1 further comprising means for delaying the working pulse pattern comprising: a shift register means containing one more register stage than the number of clock pulses per pulse pattern and to one input of which a test pulse pattern or a working pulse pattern to be delayed is applied and to another input of which the clock pulses are applied; a binary counter; first logic circuit means having inputs selectively connected to the respective outputs of said stages of said shift register means for providing a counting pulse to said counter upon the detection of one type of pulse pattern in said shift register means and for providing an erase pulse to said counter upon the detection of another type of pulse pattern in said shift register means; and second logic circuit means selectively connected to the respective outputs of the stages of said counter for terminating the delay after a predetermined count of said counter corresponding to a predetermined number of like pulse patterns.

Claim 13

Dependent Claim 61 words

A memory device as defined in claim 11 wherein said means for delaying provides a switch-on delay; and wherein said first logic circuit means is responsive to the detection of said test pulse pattern for providing said erase signal for said counter and is responsive to the detection of a working pulse pattern for providing said counting signal for said counter.

Claim 14

Dependent Claim 206 words

A memory device as defined in claim 12 wherein said working pulse patterns include an ''''on'''' order pulse pattern, an ''''off'''' order pulse pattern and an ''''acknowledgement'''' pulse pattern which is a composite of said ''''on'''' and ''''off'''' pulse pattern; wherein said first logic circuit means includes fifth and sixth AND circuits for detecting the presence of said ''''on'''' and ''''off'''' working pulse paterns respectively in said first register means with a delay of one clock pulse, a fifth OR circuit connected to the outputs of said fifth and sixth AND circuits and having its output connected to one input of a seventh AND circuit whose output is connected to the input of said counter; and wherein said second logic circuit means includes an eighth AND circuit having its inputs selectively connected to the outputs of said counter for detecting said predetermined count in said counter and its output connected to one input of a ninth AND circuit to whose other input is supplied said acknowledgement pulse pattern signal; and eighth AND circuit additionally having a negated output which is connected to a second input of said seventh AND circuit, whereby sAid counter receives a counting pulse with the first clock pulse of a pulse pattern.

Claim 15

Dependent Claim 46 words

A memory device as defined in claim 13 wherein said first logic circuit means includes means for providing an erase signal to said counter when said test pulse pattern is being fed to said shift register on the last clock pulse of said test pulse pattern.

Claim 16

Dependent Claim 40 words

A memory device as defined in claim 14 wherein said second logic circuit means includes means for emitting an output signal when said test pulse pattern is being fed to said shift register means only when said counter is erased.

Claim 17

Dependent Claim 163 words

A memory device as defined in claim 15 wherein said second logic circuit means further includes a tenth AND circuit having its inputs connected to the stages of said counter for providing an output when said counter is erased; an eleventh AND circuit having its inputs connected to said negated output of said eighth AND circuit, a negated output of said tenth AND circuit and a line supplying said test pulse pattern; the outputs of said ninth, tenth and eleventh AND circuits being coupled via an OR circuit to one input of a twelfth AND circuit, to the other input of which is applied the working pulse and test pulse patterns, and whose output constitutes the output of said delay means, whereby when any of said working pulse patterns is being supplied to the input of said shift register means, said test pulse pattern will be supplied during the delay period only when said eighth and tenth AND circuits have not switched through.

Claim 18

Dependent Claim 91 words

A memory device as defined in claim 16 wherein when one of said working pulse patterns is being fed to said shift register means and the delay period has expired, said eighth and ninth AND circuits will switch through and send the acknowledgement signal pulse pattern to said twelfth AND circuit whereby the pulse pattern being fed to said shift register means will be emitted at the output of said twelth AND circuit in synchronism with the clock pulse at the beginning of the pulse pattern following after the delay time.

Claim 19

Dependent Claim 63 words

A memory device as defined in claim 17 wherein when the signal being supplied to said shift register means is changed from one of said working pulse patterns to said test pulse pattern, said test pulse pattern appears at said output of said 12 AND circuit without delay and said delaying means is reset during the first pulse of said test pulse pattern.

Claim 20

Dependent Claim 75 words

A memory device as defined in claim 11 wherein said means for delaying provides a switch-off delay; wherein the said one input of said shift register means is connected to said signal input means of said shift register of said memory device; and wherein the output of said second logic circuit means, and hence the output of said delay means, is connected to said erase input means of said shift register of said memory device.

Claim 21

Dependent Claim 63 words

A memory device as defined in claim 19 wherein said first logic circuit means is responsive to the detection of one of said working pulse patterns in said shift register means for providing an erase pulse to said counter and is responsive to the detection of a test pulse pattern in said shift register means for providing a counting pulse to said counter.

Claim 22

Dependent Claim 174 words

A memory device as defined in claim 20 wherein: said second logic circuit means includes a fifth AND circuit having its inputs selectively connected to the outputs of said counter for detecting said predetermined count and its output connected to one input of a sixth AND circuit to whose other input is supplied said erase signal pattern, the output of said sixth AND circuit being connected to said erase input means of said shift register; and said first logic circuit means includes a seventh AND circuit whose inputs are connected to the outputs of the register stages of said shift register means for detecting the presence of said test pulse pattern in said shift register means, and its output connected to the input of said counter, and seventh AND circuit having a further input Connected to a negated output of said fifth AND circuit, whereby when said test pulse pattern is being fed to said memory device a counting signal is delivered to said counter at each first clock pulse of the pulse pattern.

Claim 23

Dependent Claim 141 words

A memory device as defined in claim 21 wherein said working pulse patterns include an ''''on'''' order pulse pattern, an ''''off'''' order pulse pattern and an ''''acknowledgement'''' pulse pattern which is a composite of said ''''on'''' and ''''off'''' pulse patterns; wherein said first logic circuit means includes eighth and ninth AND circuits for detecting the presence of said ''''on'''' and ''''off'''' working pulse patterns respectively in said shift register means with a shift in phase of one clock pulse, a fifth OR circuit connected to the outputs of said eighth and ninth AND circuits and having its output connected to said erase input of said counter whereby when one of said working pulse patterns is being supplied to said memory device, an erase pulse is fed to said counter at the beginning of every first clock pulse of a pulse pattern.

Claim 24

Dependent Claim 36 words

A memory device as defined in claim 22 wherein when a delay of x patterns is desired, said fifth AND circuit is connected to said counter so that it will switch through after x-1 pulse patterns.

Claim 25

Dependent Claim 45 words

A memory device as defined in claim 23 wherein at the first clock pulse of the last pulse pattern to be delayed after said fifth AND circuit has switched through, said input of said counter is blocked and said memory device is enabled for erasure.

Claim 26

Dependent Claim 27 words

A memory device as defined in claim 24 wherein after the last clock pulse of the last pulse pattern to be delayed, said memory device is erased.

Claim 27

Dependent Claim 32 words

A memory device as defined in claim 25 wherein when said test pulse pattern is supplied to said memory device, said counter remains occupied and said fifth AND circuit remains switched through.

Claim 28

Dependent Claim 55 words

A memory device as defined in claim 26 wherein after completion of the first pulse pattern after the pulse pattern supplied to said memory device changes from said test pulse pattern to one of said working pulse patterns, said counter is erased at the beginning of the first clock pulse of the next pulse pattern.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1978-12-08	1979-06-09	1979-12-09	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1982-12-08	1983-06-09	1983-12-09	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	1986-12-08	1987-06-09	1987-12-09	$7700.00	Window Closed / Lapsed

Memory device

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