Logic circuit having common load element

Claim 1

A logic circuit having first and second clock controlled logic stages, each logic stage comprising: a depletion type load MISFET having a drain electrode connected to a first terminal, a source electrode connected to a second terminal and a gate electrode connected to said second terminal; a first logic block connected between said second terminal and a third terminal, said first logic block comprising at least one first MISFET having a gate electrode, a drain electrode electrically connected to said second terminal and a source electrode electrically connected to said third terminal; a second logic block connected between said second terminal and a fourth terminal, said second logic block comprising at least one second MISFET having a gate electrode, a drain electrode electrically connected to said second terminal and a source electrode electrically connected to said fourth terminal; said depletion load MISFET acting as a common load for the transistors in said first and second logic blocks; a third MISFET having a gate electrode, a drain electrode connected to said third terminal and a source electrode connected to a ground terminal; a fourth MISFET having a gate electrode, a drain electrode connected to said fourth terminal and a source electrode connected to the ground terminal; a fifth MISFET having a gate electrode and two output electrodes, one of said output electrodes being connected to said second terminal and the other output electrode being connected to the gate electrode of said at least one second MISFET in said second logic block; a sixth MISFET having a gate electrode and two output electrodes, one of the output electrodes being connected to the second terminal; means for applying an electrical potential to said first terminal; means for applying a first clock pulse signal simultaneously to the gate electrodes of said third MISFET and said fifth MISFET; means for applying a second clock pulse signal simultaneously to the gate electrodes of said fourth MISFET and said sixth MISFET, said second clock pulse signal being different from said first clock pulse signal in phase; and means for applying an input signal to the gate electrode of said first MISFET, wherein said third and fourth MISFETs, respectively, of said first logic stage are the third and fourth MISFETs of said second logic stage.