Current mode carry look-ahead array

Claim 2

A current mode logic carry look-ahead array for use with up to six arithmetic/logic circuits, each arithmetic/logic circuit processing a limited number of bits of binary data in response to an operation code (M1-M16), a carry input (C), and input data (A1-A8, B1-B8), and producing output data (F1-F8) and carry generate (Gi) and carry propagate (Pi) signals, said carry lookahead array comprising a plurality of logic circuits for receiving the carry generate (Gi) and carry propagate (Pi) signals from said arithmetic/logic circuits and the initial carry-in (Cin) signal and simultaneously producing carry signals for the arithmetic/logic circuits in accordance with the following equations: C1 (G0)+(P0.C0) C2 (G1)+(P1.G0)+(P1.P0.C0) C3 (G2)+(P2.G1)+(P2.P1.G0)+(P2.P1.P0.C0) C4 (G3)+(P3.G2)+(P3.P2.G1)+(P3.P2.P1.G0) +(P3.P2.P1.P0.C0) C5 (G4)+(P4.G3)+(P4.P3.G2)+(P4.P3.P2.G1) +(P4.P3.P2.P1.G0)+(P4.P3.P2.P1.P0.C0)

Claim 3

A current mode logic carry look-ahead array as defined by claim 1 wherein each of said logic circuits comprises soft saturating current mode logic gates having an output voltage range limited to approximately 1/2 volt.

Claim 4

A current mode logic carry look-ahead array as defined by claim 1 and further including a second plurality of logic circuits for producing carry generate (Gout) and carry propagate (Pout) signals, for use with other carry look-ahead arrays, in accordance with the following equations: Gout (G5)+(P5.G4)+(P5.P4.G3)+(P5.P4.P3.G2) + (P5.P4.P3.P2.G1)+(P5.P4.P3.P2.P1.G0) Pout (P5.P4.P3.P2.P1.P0)

Claim 5

A current mode logic carry look-ahead array as defined by claim 2 wherein each of said plurality of circuits comprises soft saturating current mode logic gates having an output voltage range limited to approximately one-half volt.

Claim 6

A current mode logic carry look-ahead array as defined by claim 4 wherein said soft saturating current mode logic gates include an upper level gate comprising a first NPN bipolar transistor and at least a second NPN bipolar transistor, means interconnecting the emitters of said first and second transistors to a common terminal, means interconnecting a current source to said common terminal, resistive means connecting the collector of said first transistor to a circuit ground potential, means connecting the collector of said second transistor to circuit ground potential, means appling a reference voltage of approximately -0.26 volt to the base of said first transistor, wHereby binary input signals of 0 volt and -0.5 volt applied to the base of said second transistor are translated to output terminals at the collectors of said first and second transistors as real and complement outputs, respectively, of either 0 volt or -0.5 volt.

Claim 7

A current mode logic carry look-ahead array as defined by claim 5 and including a third NPN bipolar transistor with emitter and collector connected in parallel with the emitter and collector of said second transistor whereby said second and third transistors provide an AND function for input signals applied to the emitters of said second and third transistors.

Claim 8

A current mode logic carry look-ahead array as defined by claim 5 wherein said means for inconnecting a current source to said common terminal comprises a lower level gate.