Transistor having emitter with high circumference-surface area ratio

Claim 2

A PLANAR TRANSISTOR COMPRISING A SEMICONDUCTOR BASE REGION, A SEMICONDUCTOR COLLECTOR REGION, AND A SEMICONDUCTOR EMITTER REGION ON A SEMICONDUCTOR SLAB, SAID EMITTER REGION BEING A SINGLE ELECTRICAL UNIT AND PERFORATED IN A SIEVE-LIKE STRUCTURE WITH A PLURALITY OF OPENINGS THEREIN, SEMICONDUCTOR PORTIONS OF SAID BASE REGION EXTENDING INTO THE OPENINGS OF SAID EMITTER REGION, SAID PORTIONS OF THE BASE REGION EXTENDING TO A SLAB SURFACE COMMON WITH SAID EMITTER REGION.

Claim 3

A planar transistor as defined in claim 1, further comprising an electrical connecting means for contacting said semiconductor portions of the base region.

Claim 4

A transistor as defined in claim 2 wherein said electrical connecting means has a finger-like structure.

Claim 5

A transistor as defined in claim 1 wherein electrical contact to the emitter zone is made by an emitter contact having a finger-like structure.

Claim 6

A transistor as defined in claim 1 wherein parts of the collector region also extend into the perforations in the emitter region.

Claim 7

A planar transistor comprising a semiconductor base region, a semiconductor collector region, and a semiconductor emitter region on a semiconductor slab, said emitter region being perforated in a sieve-like structure, semiconductor portions of said base region extending into the perforations of said emitter region, semiconductor portions of said collector region extending into said semiconductor portions of the base region, said portions of the collector and base regions extending to a slab surface common with said emitter region.

Claim 8

A planar transistor comprising a semiconductor base region, a semiconductor collector region, and a semiconductor emitter region on a semiconductor slab, said emitter region being perforated in a sieve-like structure, semiconductor portions of said base region extending into the perforations of said emitter region, semiconductor portions of said collector region extending into said semiconductor portions of the base region, said portions of the collector and base regions extending to a slab surface common with said emitter region.

Claim 9

A planar transistor as defined in claim 6, further comprising an electrical connecting means for contacting said semiconductor portions of the base region.

Claim 10

A semiconductor device comprising a semiconductor substrate of a first conductivity type having a principal surface; a first semiconductive region formed in the principal surface of said substrate and having a second conductivity type opposite to the first conductivity type; a second semiconductive region of the first conductivity type formed in said first semiconductive region like a lattice dividing the principal surface of said first semiconductive region into a plurality of independent portions and surrounding each of them, the second region having a depth smaller than that of the first region, the periphery of the lattice being surrounded by said first semicoNductive region; a first conductive layer connected with said second semiconductive region on the principal surface; and a second conductive layer connected with said first semiconductive region on the principal surface.

Claim 11

A semiconductor device comprising a semiconductor substrate of a first conductivity type having a principal surface; a first semiconductive region formed in the principal surface of said substrate and having a second conductivity type opposite to the first conductivity type; a second semiconductive region of the first conductivity type formed in said first semiconductive region like a lattice dividing the principal surface of said first semiconductive region into a plurality of independent portions and surrounding each of them, the second region having a depth smaller than that of the first region, the periphery of the lattice being surrounded by said first semicoNductive region; a first conductive layer connected with said second semiconductive region on the principal surface; and a second conductive layer connected with said first semiconductive region on the principal surface.

Claim 12

A semiconductor device according to claim 8, wherein said semiconductor substrate forms a collector, said first semi-conductive region forms a base and said second semiconductive region forms an emitter.

Claim 13

A semiconductor device according to claim 8, wherein said second conductive layer is connected to all of said independent portions of said first semiconductive regions.