Patent US3922647A successfully refreshed from Google Patents.
US3922647A
Expired / Lapsed
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External exclusive OR type circuit for inverting cell MOS RAM
Assignee: Motorola Solutions Inc
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Filing: 1974-06-03
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Granted: 1975-11-25
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Expires: 1994-06-03
Abstract
Abstract External Exclusive OR type circuitry is coupled to an MOS RAM utilizing inverting storage cells and a data control register associated therewith. Bit sense lines of the RAM are coupled to a first terminal of the RAM by a first coupling circuit and the data control line is coupled to a second terminal of the RAM by a second coupling circuit. The external Exclusive OR type circuitry has inputs connected to the first and second terminals of the MOS RAM. In one embodiment, a metal masking option utilized during fabrication of the MOS RAM chip connects the bit sense lines and the data control line to an internal Exclusive OR type output circuit instead of to the first and second coupling circuits, in which case the external Exclusive OR type circuitry is not utilized. Use of the external Exclusive OR circuitry option provides a shorter access time for the RAM.
Inventors
- 👤 Jr Bernard D Broeker
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 17:43
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4096; G11C11/403; G11C11/405; G11C11/406
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
112 words
In a semiconductor random access memory includIng an MOS chip having an array of inverting storage cells and a plurality of data control cells coupled to said array, a data control conductor, said data control cells being coupled to said data control conductor, a bit sense conductor, a plurality of said array of inverting storage cells being coupled to said bit sense conductor, said semiconductor random access memory comprising external Exlusive OR-type circuit means coupled to said bit sense line and said data control conductor for producing an output data signal by comparing a first signal coupled from said data control conductor and a second signal coupled from said bit sense line.
Claim 2
Dependent Claim
112 words
In a semiconductor random access memory includIng an MOS chip having an array of inverting storage cells and a plurality of data control cells coupled to said array, a data control conductor, said data control cells being coupled to said data control conductor, a bit sense conductor, a plurality of said array of inverting storage cells being coupled to said bit sense conductor, said semiconductor random access memory comprising external Exlusive OR-type circuit means coupled to said bit sense line and said data control conductor for producing an output data signal by comparing a first signal coupled from said data control conductor and a second signal coupled from said bit sense line.
Claim 3
Dependent Claim
39 words
The semiconductor random access memory of claim 1 wherein said data control conductor is coupled to said external Exclusive OR circuit means by a first buffer circuit having an output coupled to a first terminal of said MOS chip.
Claim 4
Dependent Claim
37 words
The semiconductor random access memory of claim 1 wherein said bit sense line is coupled to said external Exclusive OR circuit means by a buffer circuit having an output coupled to said terminal of said MOS chip.
Claim 5
Dependent Claim
41 words
The semiconductor random access memory as recited in claim 2 wherein said bit sense line is coupled to said external Exclusive OR circuit means by a second buffer circuit having an output coupled to a second terminal of said MOS chip.
Claim 6
Dependent Claim
24 words
The semiconductor random access memory as recited in claim 4 wherein said external Exclusive OR circuit means is on a bipolar integrated circuit chip.
Claim 7
Dependent Claim
116 words
An MOS random access memory chip including an array of inverting MOS storage cells, a plurality of data control cells connected to said array, and a data control conductor coupled to said data control cells, a bit sense conductor coupled to a plurality of said storage cells comprising: first circuit means coupled to said data control conductor for coupling a second signal representative of a state of a selected data control cell to a first terminal of said MOS random access memory chip; and, second circuit means coupled to said bit sense conductor for coupling a second signal representative of a state of a selected MOS storage cell to a second terminal of said MOS chip.
Claim 8
Dependent Claim
116 words
An MOS random access memory chip including an array of inverting MOS storage cells, a plurality of data control cells connected to said array, and a data control conductor coupled to said data control cells, a bit sense conductor coupled to a plurality of said storage cells comprising: first circuit means coupled to said data control conductor for coupling a second signal representative of a state of a selected data control cell to a first terminal of said MOS random access memory chip; and, second circuit means coupled to said bit sense conductor for coupling a second signal representative of a state of a selected MOS storage cell to a second terminal of said MOS chip.
Claim 9
Dependent Claim
107 words
In a MOS random access memory chip including an array of MOS storage cells, a plurality of data control cells coupled to said MOS storage array, a data control conductor coupled to said data control cells, a bit sense conductor coupled to a plurality of said MOS storage cells comprising, output means coupled to said data control conductor and said bit sense conductor for optionally Exclusive OR''ing a signal on said data control conductor and a signal on said bit sense conductor or coupling signals on said data control conductor and said bit sense conductor to first and second terminals of said MOS random access memory chip.
Claim 10
Dependent Claim
107 words
In a MOS random access memory chip including an array of MOS storage cells, a plurality of data control cells coupled to said MOS storage array, a data control conductor coupled to said data control cells, a bit sense conductor coupled to a plurality of said MOS storage cells comprising, output means coupled to said data control conductor and said bit sense conductor for optionally Exclusive OR''ing a signal on said data control conductor and a signal on said bit sense conductor or coupling signals on said data control conductor and said bit sense conductor to first and second terminals of said MOS random access memory chip.
References Cited (Backward Citations)
US3736574A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-11-24 | 1979-05-26 | 1979-11-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-11-24 | 1983-05-26 | 1983-11-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-11-24 | 1987-05-26 | 1987-11-25 | $7700.00 | Window Closed / Lapsed |