Differential amplifier circuit

Claim 2

A balanced differential amplifier circuit comprising: A. a first section comprising first transistor means having base, emitter and collector electrodes; B. a second section differentially-connected with respect to said first section and comprising second transistor means having base, emitter and collector electrodes, the effective emitter junction area of one of said first and second transistor means being larger than the effective emitter junction area of the other transistor means by a factor n; C. means for applying bias potentials to the base electrodes of said transistor means; and D. a resistor connected between base electrodes of said transistor means of said first and second sections, said resistor having a resistance value which is a function of said factor n, so that the current flowing through said first section is equal to the current flowing through said second section in the absence of an input signal applied thereto.

Claim 3

A balanced differential amplifier circuit according to claim 1 in which said first transistor means comprises a plurality of parallel-connected transistors n times as great in number than said second transistor means.

Claim 4

A balanced differential amplifier circuit according to claim 1 in which said first section comprises a multi-emitter type transistor having n times as many emitters as the second transistor means.

Claim 5

A balanced differential amplifier circuit according to claim 1 in which said resistor is a squeeze resistor.

Claim 6

A balanced differential amplifier circuit comprising: A. first and second differentially-connected sections, each comprising transistor means comprising base, emitter and collector electrodes, the effective emitter junction area of one of said transistor means being larger than the effective emitter junction area of the other transiStor means by a factor n; B. means for supplying an input signal to the base of the transistor means of said first section; C. means for connecting the emitters of the transistors of said first and second sections with each other; D. output terminal means for deriving an output signal from the collector electrode of the transistor of one of said first and second sections; E. connecting means comprising a resistor connected in series between the base electrodes of the transistor means of said first and second sections, said resistor having a resistance value equal to (n-1) Beta /ngm, where Beta is the amplification factor of each transistor means and gm is the mutual conductance of each transistor means; and F. biasing means connected to the base electrode of the transistor means of one of said first and second sections and for applying a bias voltage to both transistor means of said first and second sections.

Claim 7

A balanced differential amplifier circuit comprising: A. first and second differentially-connected sections, each comprising transistor means comprising base, emitter and collector electrodes, the effective emitter junction area of one of said transistor means being larger than the effective emitter junction area of the other transiStor means by a factor n; B. means for supplying an input signal to the base of the transistor means of said first section; C. means for connecting the emitters of the transistors of said first and second sections with each other; D. output terminal means for deriving an output signal from the collector electrode of the transistor of one of said first and second sections; E. connecting means comprising a resistor connected in series between the base electrodes of the transistor means of said first and second sections, said resistor having a resistance value equal to (n-1) Beta /ngm, where Beta is the amplification factor of each transistor means and gm is the mutual conductance of each transistor means; and F. biasing means connected to the base electrode of the transistor means of one of said first and second sections and for applying a bias voltage to both transistor means of said first and second sections.