Counter circuit using current source

Claim 2

A circuit including in combination: first and second voltage supply terminals; a charge storage capacitor; a constant current source coupled in series with said charge storage capacitor between said first and second voltage supply terminals in a charging path for said charge storage capacitor for charging said charge storage capacitor for a predetermined time interval over a predetermined range of amplitude; a normally non-conductive comparator circuit comprising first and second transistors of opposite conductivity type, each of said transistors having base, collector, and emitter electrodes, the emitter of said first transistor being coupled with said first voltage supply terminal, the collector of said first transistor being coupled at a junction with the base of said second transistor to form a first input of said comparator circuit, the collector of said second transistor connected to the base of said first transistor, and the emitter of said second transistor comprising both a second input of said comparator circuit and a discharge path connection for said charge storage capacitor; a voltage divider connected between said first and second supply terminals for supplying a reference voltage coupled to said first input of said comparator circuit for establishing a reference switching level therefor; means for coupling said charge storage capacitor with said second input of said comparator circuit means; means for supplying pulses having a predetermined maximum amplitude and a predetermined frequency to the first input of said comparator circuit during said predetermined time interval, the maximum amplitude of the applied pulses being less than the predetermined range of amplitude over which said charge storage capacitor is charged, the comparator circuit being rendered conductive upon the coincidence of a predetermined charge attained by said charged storage capacitor and the application of one of said pulses to discharge said charge storage capacitor.

Claim 3

A counter circuit providing an output pulse in response to a predetermined number of input pulses of equal duration including in combination: first and second voltage supply terminals; a charge storage capacitor having first and second terminals, the first terminal of which is coupled with the first voltage supply terminal; a differential switch including first and second transistors, each having collector, base and emitter electrodes, with the collector electrode of the first transistor coupled with the first voltage supply terminal and the collector electrode of the second transistor coupled with the second terminal of the charge storage capacitor; a constant current source transistor coupled between the second voltage supply terminal and the emitters of the first and second transistors; means for applying a reference biasing potential to the base of at least one of the first and second transistors; means for applying input pulses to the base of at least one of the first and second transistors to alternately render the first and second transistors conductive and non-conductive to charge the charge storage capacitor by the same amount in each of a number of discrete steps; and comparator circuit means having first and second inputs and coupled with the second terminal of the charge storage capacitor and responsive to a predetermined charge attained by the charge storage capacitor for providing a discharge path for the charge storage capacitor; means for supplying a reference potential to the first input of the comparator circuit means to establish said predetermined charge at which the discharge path is provided for the charge storage capacitor; means for coupling the second Terminal of the charge storage capacitor to the second input of the comparator means; and means for applying additional pulses at a frequency equal to or greater than the highest repetition frequency of the input pulses to one of the first and second inputs of the comparator circuit means, the magnitude of the additional pulses being no greater than the maximum discrete increment of charge attained by the charge storage device in response to application of an input pulse to the differential switch.

Claim 4

A counter circuit providing an output pulse in response to a predetermined number of input pulses of equal duration including in combination: first and second voltage supply terminals; a charge storage capacitor having first and second terminals, the first terminal of which is coupled with the first voltage supply terminal; a differential switch including first and second transistors, each having collector, base and emitter electrodes, with the collector electrode of the first transistor coupled with the first voltage supply terminal and the collector electrode of the second transistor coupled with the second terminal of the charge storage capacitor; a constant current source transistor coupled between the second voltage supply terminal and the emitters of the first and second transistors; means for applying a reference biasing potential to the base of at least one of the first and second transistors; means for applying input pulses to the base of at least one of the first and second transistors to alternately render the first and second transistors conductive and non-conductive to charge the charge storage capacitor by the same amount in each of a number of discrete steps; and comparator circuit means having first and second inputs and coupled with the second terminal of the charge storage capacitor and responsive to a predetermined charge attained by the charge storage capacitor for providing a discharge path for the charge storage capacitor; means for supplying a reference potential to the first input of the comparator circuit means to establish said predetermined charge at which the discharge path is provided for the charge storage capacitor; means for coupling the second Terminal of the charge storage capacitor to the second input of the comparator means; and means for applying additional pulses at a frequency equal to or greater than the highest repetition frequency of the input pulses to one of the first and second inputs of the comparator circuit means, the magnitude of the additional pulses being no greater than the maximum discrete increment of charge attained by the charge storage device in response to application of an input pulse to the differential switch.

Claim 5

The combination according to claim 2 wherein the comparator circuit means includes third and fourth transistors of opposite conductivity type, each having collector, base, and emitter electrodes, and wherein the means for supplying the reference voltage includes a voltage divider connected between the first and second voltage supply terminals, the emitter of the third transistor being coupled with the first supply terminal, the collector of the third transistor being connected to the base of the fourth transistor at a junction comprising the first input to the comparator circuit means the base of the third transistor being connected to the collector of the fourth transistor, and the emitter of the fourth transistor comprising the second input of the comparator circuit means.

Claim 6

A counter circuit providing an output pulse in response to a predetermined number of cycles of an input signal of a predetermined frequency and having a first and second condition on each cycle thereof including in combination: a charge storage device; a signal operated active constant current source means coupled in a series charging path with the charge storage device; means for applying the input signal to the constant current source means to render the constant current source means alternately conductive and non-conductive in response to said first and second conditions, respectively, to charge the charge storage device from the current source means by the same incremental charge in each of a number of discrete steps; normally non-conductive switch means coupled in a discharge path with the charge storage device and having at least one input coupled to respond to the potential stored by the charge storage device; means for applying pulses to the switch means at a frequency equal to or greater than the frequency of the input signal and having an amplitude less than the incremental charge attained by the charge storage device in each discrete step to render the switch means conductive in response to the simultaneous application thereto of a predetermined charge on the charge storage device and one of said pulses.

Claim 7

A counter circuit providing an output pulse in response to a predetermined number of cycles of an input signal of a predetermined frequency and having a first and second condition on each cycle thereof including in combination: a charge storage device; a signal operated active constant current source means coupled in a series charging path with the charge storage device; means for applying the input signal to the constant current source means to render the constant current source means alternately conductive and non-conductive in response to said first and second conditions, respectively, to charge the charge storage device from the current source means by the same incremental charge in each of a number of discrete steps; normally non-conductive switch means coupled in a discharge path with the charge storage device and having at least one input coupled to respond to the potential stored by the charge storage device; means for applying pulses to the switch means at a frequency equal to or greater than the frequency of the input signal and having an amplitude less than the incremental charge attained by the charge storage device in each discrete step to render the switch means conductive in response to the simultaneous application thereto of a predetermined charge on the charge storage device and one of said pulses.