US3916384A Expired / Lapsed US ⏱️ 0.0 years remaining

Communication switching system computer memory control arrangement

Assignee: AG Communication Systems Corp

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Filing: 1973-06-15

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Granted: 1975-10-28

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Expires: 1993-06-15

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Abstract

Abstract A computer memory control arrangement includes a plurality of input/output ports for permitting a central processor connected to one port to access a main memory to obtain or store data or instructions for enabling the central processor to effect call processing or maintenance operations and for permitting the transfer of programs to the main memory from a drum control memory including at least one drum control unit connected to a another port. A port select circuit permits port selection on a priority basis when memory requests are received over more than one port simultaneously. In addition, while the memory request for a selected port is being processed, the selection of a second port for a second memory request can be initiated before the end of the memory cycle for the first selected port. Each drum control unit has an assigned block of data storage locations serving as an initialization table within the computer main memory. The central processor can effect a transfer of instructions and/or data words from a designated drum control unit to the main memory by accessing the main memory and storing instructions in the initialization table for the designated drum control unit and thereafter sending an instruction to the drum control unit to enable the drum control unit to access its initialization table and effect the transfer indicated therein. Initialization table protection is provided by a circuit which prevents one drum control unit from writing into an initialization table of another drum control unit. A read only memory circuit prevents the drum control units and the central processor from writing into a preselected block of data storage locations of the main memory. In addition, a software protect read only memory circuit prevents the central processor from writing into blocks of data storage locations of the computer main memory while permitting the drum control units to write into such locations.

Inventors

👤 Richard D Fleming
👤 Kasimir W Schild

Bibliographic Details

Application Number —

Jurisdiction US

Data Source google_patents

Last Synchronized 2026-10-26 11:41

CPC Classifications

H; H04; H04Q; H04Q3/00; H04Q3/42; H04Q3/54; H04Q3/545; H04Q3/54508; H04Q3/54516; G; G06; G06F; G06F12/00; G06F12/14; G06F12/1416; G06F12/1425; G06F13/00; G06F13/14; G06F13/16; G06F13/18; H04Q2213/00; H04Q2213/1305; H04Q2213/13109; H04Q2213/13376

Claims Analysis

Total Claims: 6

Claim 1

Independent Claim 201 words

In a communication system, a memory control arrangement including a central processor means, main memory means having a plurality of addressable data storage locations for storing data and program instructions for said central processor means, at least one auxiliary memory means for storing further instructions for said central processor means and memory control means for providing memory access control to permit the transfer of data between said main memory means either and said central processor means or said auxiliary memory means, said memory control means having a plurality of input/output ports including separate ports for said auxiliary memory means and said central processor means, port select means including first means for initiating a first main memory access cycle to enable one of said auxiliary memory means or said central processor means to address a data storage location of said main memory means to permit readout or modification of the program instruction or data stored at the addressed main memory means location, and second means for controlling said first means to initiate a second main memory access cycle for a different one of said auxiliary memory means or said central processor means prior to the termination of said first memory access cycle.

Claim 2

Dependent Claim 201 words

Claim 3

Dependent Claim 84 words

A system as set forth in claim 1 wherein said first means includes port select primary register means including an individual port select primary register for each port of said memory control means, each of said port select primary registers having a plurality of inhibit inputs, the inhibit inputs of said port select primary registers being interwired to provide selection of a port on a priority basis in the event of simultaneous memory requests from said auxiliary memory means and said central processor means.

Claim 4

Dependent Claim 215 words

A system as set forth in claim 1 wherein said first means includes port select primary register means including an individual port select primary register for each of said ports and said second means includes port select secondary register means including an individual port select secondary register for each of said port select primary registers, the one of said port select primary registers of the selected port being set responsive to the receipt of a memory request for such port to initiate a memory access cycle to permit access of the main memory means by said selected port, said one port select primary regisTer inhibit being operable when set to the remaining port select primary registers to preclude the initiation of a further memory access cycle by one of the remaining ports while said one port select primary register is set, the port select secondary register corresponding to said one port select primary register being set by said one port select primary register at a predetermined time during said first memory access cycle, and said one port select primary register being reset at such time to enable selection of a different one of said ports to permit a further memory access cycle to be initiated prior to the termination of the first memory access cycle.

Claim 5

Dependent Claim 35 words

A system as set forth in claim 3 wherein said second means includes means for inhibiting said one port select primary register until a second port has been selected, for a further memory access cycle.

Claim 6

Dependent Claim 21 words

A system as set forth in claim 4 wherein said auxiliary memory means includes at least one rotating drum memory means.

References Cited (Backward Citations)

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USPTO Annuity & Maintenance Windows

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1978-10-27	1979-04-28	1979-10-28	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1982-10-27	1983-04-28	1983-10-28	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	1986-10-27	1987-04-28	1987-10-28	$7700.00	Window Closed / Lapsed

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