Multi-layer semiconductor device

Claim 2

A MULTI-LAYER SIMICONDUCTOR DEVICE COMPRISING A SEMICONDUCTOR BODY INCLUDING THEREIN FOUR CONTIGUOUS LAYERS, ADJACENT ONES OF SAID LAYERS HAVING A CONDUCTIVITY TYPE DIFFERENT FROM EACH OTHER, AND A PAIR OF MAIN ELECTRODES IN LOW OHMIC CONTACT WITH THE UPPERMOST AND LOWERMOST LAYERS RESEPECTIVITY OF SAID SIMICONDUCTOR BODY, WHEREIN THE UPPERMOST LAYER IN SAID SIMICONDUCTOR BODY COMPRISES A MAIN REGION IN CONTACT WITH SAID MAIN ELECTRODE AND AN AUXILLIARY REGION NOT IN CONTACT WITH SAID MAIN ELECTRODE AND ELECTRICALLY ISOLATED FROM SAID MAIN REGION BY A GROOVE EXTENDING TO THE ADJOINING LAYER OF OPPOSITE CONDUCTIVITY TYPE, SAID AUXILLIRY REGION HAVING A CONDUCTOR LAYER DISPOSED EXCLUSIVELY ON THE SURFACE THEREOF, A SMALL REGION OF THE SAME CONDUCTIVITY TYPE AS THAT OF SAID UPPERMOST LAYER BEING PROVIDED BETWEEN SAID MAIN REGION AND SAID AUXILLIARY REGION AT A SPOT ALONG THE BOUNDARY THEREBETWEEN TO THEREBY CONNECT SAID MAIN REGION WITH SAID AUXILLIARY REGION, WHEREIN AN INTERMEDIATE REGION OF A CONDUCTIVITY TYPE OPPOSITE TO THAT OF SAID ADJOINING LAYER AND CONNECTED WITH SAID ADJOUNING LAYER BUT ISOLATED FROM SAID MAIN AND AUXILIARY REGION IS PROCIDED IN SAID GROOVE AT A PLACE REMOTE FROM SAID SMALL REGION AND A CONTROL ELECTRODE IS ATACHED TO SAID INTERMEDIATE REGION.

Claim 3

A multi-layer semiconductor device comprising a semiconductor body including therein four contiguous layers, adjacent ones of said layers having a conductivity type different from each other, and a pair of main electrodes in low ohmic contact with the uppermost and lowermost layers respectively of said semiconductor body, wherein the uppermost layer in said semiconductor body comprises a main region in contact with said main electrode and an auxiliary region not in contact with said main electrode and electrically isolated from said main region by a groove extending to the adjoining layer of opposite conductivity type, said auxiliary region having a conductor layer disposed exclusively on the surface thereof, a small region of the same conductivity type as that of said uppermost layer being provided between said main region and said auxiliary region at a spot along the boundary therebetween to thereby connect said main region with said auxiliary region, wherein said auxiliary region is surrounded by said main region, and an intermediate region of a conductivity type opposite to that of said adjoining layer and connected with said adjoining layer but isolated from said main and auxiliary regions is provided in said groove at a place remote from said small region, and further a control electrode is attached to the surface of said intermediate region.

Claim 4

A multi-layer semiconductor device comprising a semiconductor body including therein four contiguous layers, adjacent ones of said layers having a conductivity type different from each other, and a pair of main electrodes in low ohmic contact with the uppermost and lowermost layers respectively of said semiconductor body, wherein the uppermost layer in said semiconductor body comprises a main region in contact with said main electrode and an auxiliary region not in contact with said main electrode and electrically isolated from said main region by a groove extending to the adjoining layer of opposite conductivity type, said auxiliary region having a conductor layer disposed exclusively on the surface thereof, a small region of the same conductivity type as that of said uppermost layer being provided between said main region and said auxiliary region at a spot along the boundary therebetween to thereby connect said main region with said auxiliary region, wherein said auxiliary region is surrounded by said main region, and an intermediate region of a conductivity type opposite to that of said adjoining layer and connected with said adjoining layer but isolated from said main and auxiliary regions is provided in said groove at a place remote from said small region, and further a control electrode is attached to the surface of said intermediate region.

Claim 5

A multi-layer semiconductor device as claimed in claim 2, wherein is provided a second auxiliary region of the same conductivity type as that of said main region, which is electrically isolated from said main region by a groove extending to said adjoining layer and surrounds said main region.

Claim 6

A multi-layer semiconductor device comprising: a semiconductor body having first and second principal surfaces on opposite sides of said body, said Body including: a first semiconductor layer of a first conductivity type, one surface of which corresponds to said first principal surface of said body; a second semiconductor layer of a second conductivity type, opposite said first conductivity type, disposed in contact with said first semiconductor layer, so as to form a first PN junction therebetween; a third semiconductor layer of said first conductivity type disposed in contact with said second semiconductor layer, so as to form, therebetween, a second PN junction; a fourth semiconductor layer of said second conductivity type disposed in contact with said third semiconductor layer, so as to form therebetween a third PN junction, one surface of said fourth layer corresponding to said second principal surface of said body, said fourth semiconductor layer including a main region, having a first prescribed circumferential configuration, disposed in contact with a first portion of said third semiconductor layer, so as to define said third PN junction, and an auxiliary region, having a second prescribed circumferential configuration, disposed in contact with a second portion of said third semiconductor layer and spaced apart from said main region by an isolation region therebetween, said isolation region comprising a groove defining the distance separating the respective opposed peripheries of said main region and said auxiliary region, and means for bridging said main region and said auxiliary region and resistively connecting said opposed peripheries of said main region and said auxiliary region together comprising a resistive region of said second conductivity type formed contiguously to said main region and said auxiliary region at only a relatively narrow spot portion of said groove therebetween, and wherein said auxiliary region has a conductor layer disposed exclusively on the surface thereof; a first principal electrode in low ohmic contact with said first semiconductor layer at the first principal surface of said body; a second principal electrode in low ohmic contact with only the main region of said fourth semiconductor layer at the second principal surface of said body; and further including a control electrode disposed within said groove and separated from each of said main and auxiliary regions while being connected to said fourth semiconductor layer.

Claim 7

A multi-layer semiconductor device comprising: a semiconductor body having first and second principal surfaces on opposite sides of said body, said Body including: a first semiconductor layer of a first conductivity type, one surface of which corresponds to said first principal surface of said body; a second semiconductor layer of a second conductivity type, opposite said first conductivity type, disposed in contact with said first semiconductor layer, so as to form a first PN junction therebetween; a third semiconductor layer of said first conductivity type disposed in contact with said second semiconductor layer, so as to form, therebetween, a second PN junction; a fourth semiconductor layer of said second conductivity type disposed in contact with said third semiconductor layer, so as to form therebetween a third PN junction, one surface of said fourth layer corresponding to said second principal surface of said body, said fourth semiconductor layer including a main region, having a first prescribed circumferential configuration, disposed in contact with a first portion of said third semiconductor layer, so as to define said third PN junction, and an auxiliary region, having a second prescribed circumferential configuration, disposed in contact with a second portion of said third semiconductor layer and spaced apart from said main region by an isolation region therebetween, said isolation region comprising a groove defining the distance separating the respective opposed peripheries of said main region and said auxiliary region, and means for bridging said main region and said auxiliary region and resistively connecting said opposed peripheries of said main region and said auxiliary region together comprising a resistive region of said second conductivity type formed contiguously to said main region and said auxiliary region at only a relatively narrow spot portion of said groove therebetween, and wherein said auxiliary region has a conductor layer disposed exclusively on the surface thereof; a first principal electrode in low ohmic contact with said first semiconductor layer at the first principal surface of said body; a second principal electrode in low ohmic contact with only the main region of said fourth semiconductor layer at the second principal surface of said body; and further including a control electrode disposed within said groove and separated from each of said main and auxiliary regions while being connected to said fourth semiconductor layer.

Claim 8

A multi-layer semiconductor device according to claim 4, wherein said control electrode is connected to said third semiconductor layer through a fifth semiconductor region of said second conductivity type disposed in contact with said third semiconductor layer, with said control electrode being disposed in contact with said fifth semiconductor region.

Claim 9

A multi-layer semiconductor device comprising: a semiconductor body having first and second principal surfaces on opposite sides of said body, said body including: a first semiconductor layer of a first conductivity type, one surface of which corresponds to said first principal surface of said body; a second semiconductor layer of a second conductivity type, opposite said first conductivity type, disposed in contact with said first semiconductor layer, so as to form a first PN junction therebetween; a third semiconductor layer of said first conductivity type disposed in contact with said second semiconductor layer, so as to form, therebetween, a second PN junction; a fourth semiconductor layer of said second conductivity type disposed in contact with said third semiconductor layer, so as to form therebetween a third PN junction, one surface of said fourth layer corresponding to said second principal surface of said body, said fourth semiconductor layer including a main region, having a first prescribed circumferential configuration, disposed in contact with a first portion of said third semiconductor layer, so as to define said third PN junction, and an auxiliary region, having a second prescribed circumferential configuratiOn, disposed in contact with a second portion of said third semiconductor layer and spaced apart from said main region by an isolation region therebetween, said isolation region comprising a groove defining the distance separating the respective opposed peripheries of said main region and said auxiliary region, and means for bridging said main region and said auxiliary region and resistively connecting said opposed peripheries of said main region and said auxiliary region together comprising a resistive region of said second conductivity type formed contiguously to said main region and said auxiliary region at only a portion of said groove therebetween, wherein each of said auxiliary region and said isolation region is arcuate in shape and said auxiliary region is resistively bridged at opposite arcuate ends thereof to said main region; a first principal electrode in low ohmic contact with said first semiconductor layer at the first principal surface of said body; and a second principal electrode in low ohmic contact with only the main region of said fourth semiconductor layer at the second principal surface of said body.

Claim 10

A multi-layer semiconductor device comprising: a semiconductor body having first and second principal surfaces on opposite sides of said body, said body including: a first semiconductor layer of a first conductivity type, one surface of which corresponds to said first principal surface of said body; a second semiconductor layer of a second conductivity type, opposite said first conductivity type, disposed in contact with said first semiconductor layer, so as to form a first PN junction therebetween; a third semiconductor layer of said first conductivity type disposed in contact with said second semiconductor layer, so as to form, therebetween, a second PN junction; a fourth semiconductor layer of said second conductivity type disposed in contact with said third semiconductor layer, so as to form therebetween a third PN junction, one surface of said fourth layer corresponding to said second principal surface of said body, said fourth semiconductor layer including a main region, having a first prescribed circumferential configuration, disposed in contact with a first portion of said third semiconductor layer, so as to define said third PN junction, and an auxiliary region, having a second prescribed circumferential configuratiOn, disposed in contact with a second portion of said third semiconductor layer and spaced apart from said main region by an isolation region therebetween, said isolation region comprising a groove defining the distance separating the respective opposed peripheries of said main region and said auxiliary region, and means for bridging said main region and said auxiliary region and resistively connecting said opposed peripheries of said main region and said auxiliary region together comprising a resistive region of said second conductivity type formed contiguously to said main region and said auxiliary region at only a portion of said groove therebetween, wherein each of said auxiliary region and said isolation region is arcuate in shape and said auxiliary region is resistively bridged at opposite arcuate ends thereof to said main region; a first principal electrode in low ohmic contact with said first semiconductor layer at the first principal surface of said body; and a second principal electrode in low ohmic contact with only the main region of said fourth semiconductor layer at the second principal surface of said body.

Claim 11

A multi-layer semiconductor device according to claim 6, wherein said auxiliary region is resistively bridged at opposite arcuate ends thereof by a relatively narrow spot portion of a resistive region of said second conductivity type.