Serial-parallel-serial ccd memory with interlaced storage

Claim 2

In a CCD memory, the combination comprising: a. a parallel CCD storage register having R channels, each channel for storing a plurality of information-bearing charge packets; b. a serial CCD input register having one storage site for each of said R channels; c. means for alternately clocking into said serial CCD input register charge packets to be stored in even and odd numbered ones of said R channels so that a first group of charge packets to be stored in even numbered channels are clocked into a first set of alternate storage sites in said serial CCD input register and a second group of charge packets to be stored in odd numbered channels are clocked into a second set of storage sites which alternate with said first set of storage sites; and d. means for transferring into said R channels the charge packets previously clocked into said first and second sets of storage sites; and e. means for concurrently stepping along said R channels the charge packets previously transferred thereto.

Claim 3

The combination of claim 1 characterized further in that said serial CCD input register comprises a semiconductive storage medium, having a dielectric layer dispOsed over said surface and a series of electrode structures distributed above said surface, each electrode structure having a metal electrode member on the surface of said dielectric layer and a doped semiconductor electrode member buried in said dielectric layer.

Claim 4

The combination of claim 2 characterized further in that said doped semiconductor member is polycrystalline silicon, said substrate is silicon, said insulating layer is silicon dioxide and said metal electrode member is aluminum.

Claim 5

The combination of claim 1 characterized further by: a. means external of said input register for temporarily storing each group of charge packets after it is clocked into said input register; and b. means for transferring each group of charge packets out of said input register and into said temporary storage means.

Claim 6

The combination of claim 4 characterized further in that said temporary storage means is comprised of a storage site at the input end of each said R channels.

Claim 7

A CCD memory comprising in combination: a. a parallel CCD storage register having R channels, each channel having a linearly extending series of storage sites for storing a plurality of information-bearing charge packets; b. a serial CCD input register having one storage site adjacent the input end of each of said R channels; c. a serial CCD output register having one storage site adjacent the output end of each of said R channels; d. means for alternately clocking into said serial CCD input register respective groups of charge packets to be stored in even and odd numbered ones of said R channels; e. means for transferring to the input end of a respective one of said R channels each charge packet previously clocked into said input register; f. means for concurrently stepping said transferred charge packets from the input ends of said channels toward their output ends; g. means for transferring said charge packets upon their arrival at the output ends of said R channels to respective ones of the storage sites in said output register; and h. means for reading out of said output register the charge packets previously transferred thereinto.

Claim 8

A CCD memory comprising in combination: a. a parallel CCD storage register having R channels, each channel having a linearly extending series of storage sites for storing a plurality of information-bearing charge packets; b. a serial CCD input register having one storage site adjacent the input end of each of said R channels; c. a serial CCD output register having one storage site adjacent the output end of each of said R channels; d. means for alternately clocking into said serial CCD input register respective groups of charge packets to be stored in even and odd numbered ones of said R channels; e. means for transferring to the input end of a respective one of said R channels each charge packet previously clocked into said input register; f. means for concurrently stepping said transferred charge packets from the input ends of said channels toward their output ends; g. means for transferring said charge packets upon their arrival at the output ends of said R channels to respective ones of the storage sites in said output register; and h. means for reading out of said output register the charge packets previously transferred thereinto.

Claim 9

The memory of claim 6 characterized further in that said memory is formed on the surface of a semiconductive wafer, the outer perimeters of said input, output, and parallel registers being defined by a common circumferential channel stopper diffused into said surface, individual ones of said R channels being defined by a plurality of parallel channel stoppers diffused into said surface and extending within said common channel stopper from said input register to said output register.

Claim 10

The memory of claim 7 characterized further in that said semiconductive wafer is covered by a dielectric layer and said parallel register includes two sets of interdigitated metal transfer electrodes on the surface of said dielectric layer and two sets of interdigitated storage electrodes buried within said dielectric layer, each electrode spanning all of said R channels.

Claim 11

The memory of claim 7 characterized further in that said input and output registers each include a plurality of storage electrodes, respective storage electrodes of said input register extending over the input ends of corresponding ones of said R channels and respective storage electrodes of said output register extending over the output ends of corresponding ones of said R channels.

Claim 12

A CCD memory in accordance with claim 9 characterized further in that: a. each of said R channels includes a temporary storage site at its input end for holding a charge packet prior to its being stepped along said channel, and b. said means for transferring charge packets to the input end of said R channels are operative to transfer the respective groups of charge packets into said temporary storage sites separately, each before the other group has been clocked into said input register.

Claim 13

In a serial-parallel-Serial CCD memory, the combination comprising: a. a serial CCD input register having a plurality of linearly extending storage sites, each defined by a separate storage electrode member; b. a parallel CCD storage register having a separate charge channel extending from and communicating at its top end with each of said storage sites; c. a serial CCD output register having a plurality of storage sites linearly extending parallel to those of said input register, each storage site of said output register communicating with the bottom end of a respective one of said charge channels; d. means for serially reading data into successive interlaced sets of said storage sites; and e. means for separately transferring data from respective ones of said interlaced sets of storage sites to said parallel CCD storage register.

Claim 14

In a serial-parallel-Serial CCD memory, the combination comprising: a. a serial CCD input register having a plurality of linearly extending storage sites, each defined by a separate storage electrode member; b. a parallel CCD storage register having a separate charge channel extending from and communicating at its top end with each of said storage sites; c. a serial CCD output register having a plurality of storage sites linearly extending parallel to those of said input register, each storage site of said output register communicating with the bottom end of a respective one of said charge channels; d. means for serially reading data into successive interlaced sets of said storage sites; and e. means for separately transferring data from respective ones of said interlaced sets of storage sites to said parallel CCD storage register.

Claim 15

The combination of claim 11 characterized further in that the storage sites of said serial input register comprise two interlaced sets of storage sites into which data are read alternately.

Claim 16

In a serial-parallel-serial CCD memory the combination comprising: a. a serial CCD input register having a set of linearly extending storage sites, each defined by a separate storage electrode member; b. a parallel CCD storage register having separate charge channels individually extending from and communicating with respective ones of said storage sites, each said channel having a column of storage sites, with corresponding sites of the respective channels forming successive rows of storage sites; c. a serial CCD output register having a set of linearly extending storage sites individually adjacent to and communicating with, respective ones of said charge channels; d. means for serially clocking into said input register N sets of charge packets in succession, each set of charge packets being clocked into a different subset of said input register storage sites, with individual members of the respective subset of storage sites being interlaced; e. means for transferring the charge packets stored in said input register into the first of said rows of storage sites; f. means for clocking charge packets along said channels toward said output register; g. means for transferring charge packets from said parallel register storage sites to said output register; and h. means for serially clocking charge packets from said output register.

Claim 17

In a serial-parallel-serial CCD memory the combination comprising: a. a serial CCD input register having a set of linearly extending storage sites, each defined by a separate storage electrode member; b. a parallel CCD storage register having separate charge channels individually extending from and communicating with respective ones of said storage sites, each said channel having a column of storage sites, with corresponding sites of the respective channels forming successive rows of storage sites; c. a serial CCD output register having a set of linearly extending storage sites individually adjacent to and communicating with, respective ones of said charge channels; d. means for serially clocking into said input register N sets of charge packets in succession, each set of charge packets being clocked into a different subset of said input register storage sites, with individual members of the respective subset of storage sites being interlaced; e. means for transferring the charge packets stored in said input register into the first of said rows of storage sites; f. means for clocking charge packets along said channels toward said output register; g. means for transferring charge packets from said parallel register storage sites to said output register; and h. means for serially clocking charge packets from said output register.