Patent US3913072A successfully refreshed from Google Patents.
US3913072A
Expired / Lapsed
US
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Digital integrated circuits
Assignee: Sinclair Research Ltd
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Filing: 1973-07-23
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Granted: 1975-10-14
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Expires: 1993-07-23
Abstract
Abstract In order to eliminate the expense of dicing an integrated circuit into chips, testing the chips, selecting, packaging and retesting the chips, the wafer is left undiced and each chip includes switching and control circuits which enable a chip to be linked to any one of its neighbours. A chain of good chips is built up by sending control signals down the existing part of the chain (which starts with one chip) to cause a new chip to be added to the chain. Test signals are then used to ascertain if the added chip is good. If it is the next chip is added; if not, the chip is disconnected and the control signals utilised to select another neighbouring chip as the added chip. Faulty chips are thus simply by-passed by the chain which is built up of good chips only to form a long shift register for example. Grids of power and clock lines are provided to all chips and a fast data line grid may be used for accessing all chips in a content addressable memory application.
Inventors
- 👤 Ivor Catt
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 12:23
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/006; G11C15/00; G11C15/04
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
134 words
A digital integrated circuit comprising a plurality of undiced regions in a semi-conductor wafer, each region having at least one set of input connections and a plurality of sets of output connections and having formed thereon a digital circuit means for operating on digital information and for transferring digital information signals and control signals, said digital circuit including a logical switching circuit, said logical switching circuit including means for coupling a set of input connections to a selected one of the sets of output connections by way of said digital circuit, the sets of output connections being connected to sets of input connections of a plurality of neighbouring regions, and the logical switching circuit of each region includiNg means responsive to certain of the control signals for changing the selected set of output connections.
Claim 2
Dependent Claim
134 words
A digital integrated circuit comprising a plurality of undiced regions in a semi-conductor wafer, each region having at least one set of input connections and a plurality of sets of output connections and having formed thereon a digital circuit means for operating on digital information and for transferring digital information signals and control signals, said digital circuit including a logical switching circuit, said logical switching circuit including means for coupling a set of input connections to a selected one of the sets of output connections by way of said digital circuit, the sets of output connections being connected to sets of input connections of a plurality of neighbouring regions, and the logical switching circuit of each region includiNg means responsive to certain of the control signals for changing the selected set of output connections.
Claim 3
Dependent Claim
24 words
A digital integrated circuit according to claim 1, wherein said digital circuit includes means for storing said digital information connected to said switching circuit.
Claim 4
Dependent Claim
24 words
A digital integrated circuit according to claim 1, wherein said digital circuit includes means for processing said digital information connected to said switching circuit.
Claim 5
Dependent Claim
26 words
A digital integrated circuit according to claim 1, wherein said digital circuit includes means for storing and processing said digital information connected to said switching circuit.
Claim 6
Dependent Claim
14 words
A digital integrated circuit according to claim 1, wherein the regions are identical regions.
Claim 7
Dependent Claim
38 words
A digital integrated circuit according to claim 1, comprising control means operative to address control signals to a succession of regions and to control the logical switching circuits of said regions to interconnect said regions in a chain.
Claim 8
Dependent Claim
84 words
A digital integrated circuit according to claim 6, wherein the control means is operative to address a control signal to the n''th region of the chain by including a numerical code in the control signal, each region of the chain including a circuit for effecting a predetermined modification of the numerical code such that the code assumes a region-identifying form at the n''th region, each region further including a circuit for recognizing the region-identifying code form and for commanding response to the control signal.
Claim 9
Dependent Claim
28 words
A digital integrated circuit according to claim 7, wherein the predetermined modification effected by each region of the chain is decrementing of the numerical value of the code.
Claim 10
Dependent Claim
36 words
A digital integrated circuit according to claim 8, wherein the numerical code furnished by the control means has the value n - 1 and the n''th region causes and responds to a continuously propagating borrow bit.
Claim 11
Dependent Claim
143 words
A digital integrated circuit according to claim 6, wherein the control means is constructed to follow a predetermined control sequence to link an additional region to the chain, said predetermined control sequence including addressing a control signal to the logical switching circuit of the preceding region of the chain, addressing a test data signal to the said additional region, receiving and checking the correctness of returned data signal, and then, if the returned signal is correct, proceeding to link a further region to the chain in like manner, but, if the returned signal is not correct, sending a further control signal to the logical switching circuit of the said preceding region of the chain to link this region to a different neighbouring, additional region and then proceeding to the addressing of the test data signal to this region and the specified ensuing steps.
Claim 12
Dependent Claim
139 words
A digital integrated circuit according to claim 10, wherein each region has a plurality of sets of input connections corresponding to the sets of output connections respectively and the logical switching circuit includes means for responding to a control signal to select one set of input connections, and wherein the control means is constructed to link the additional region to the chain by addressing a control signal to the logical switching circuit of the preceding region of the chain to select one set of output connections leading to a neighbouring region located in a predetermined direction relative to the preceding region and then by addressing a control signal to the logical switching circuit of the said additional region to select that set of input connections which is connected to the selected set of output connections of the preceding region.
Claim 13
Dependent Claim
113 words
A digital integrated circuit according to claim 6, wherein the neighbouring regions of any one region are identified by the directions thereto from the one region, which directions form a cyclic clockwise or anticlockwise sequence, and wherein the control means is constructed to link an adDitional region to the chain by addressing a control signal to the logical switching circuit of the preceding region of the chain such as to select the set of output connections corresponding to the direction which is next in the cyclic sequence from the direction of the pre-preceding region of the chain relative to the said preceding region, thereby to tend to form a spiral chain of regions.
Claim 14
Dependent Claim
129 words
A digital integrated circuit according to claim 10, wherein the neighbouring regions of any one region are identified by the directions thereto from the one region, which directions form a cyclic clockwise or anticlockwise sequence, and wherein the control means is constructed to link an additional region to the chain by addressing a control signal to the logical switching circuit of the preceding region of the chain such as to select the set of output connections corresponding to the direction which is next in the cyclic sequence from the direction of the pre-preceding region of the chain relative to the said preceding region, thereby to tend to form a spiral chain of regions, and wherein the said further region is again in the direction next in the cyclic sequence.
Claim 15
Dependent Claim
93 words
A digital integrated circuit according to claim 12, comprising a line for sending synchronizing signals to all regions and wherein each region comprises a direction determining circuit responsive to the synchronizing signals to select the sets of connections in cyclic sequence, corresponding to the cyclic sequence of directions, until the region is incorporated in the chain, and wherein the control means is constructed to select a direction at a region by addressing a control signal thereto at the time that the direction determining circuit is in the state corresponding to the required direction.
Claim 16
Dependent Claim
78 words
A digital integrated circuit according to claim 6, wherein each set of input connections and each set of output connections comprise forward connections between which extends a forward data flow path and further comprise return connections between which extends a return data flow path, the logical switching circuits connecting the forward data flow path to the return data flow path so long as a region is not incorporated in the chain other than as the last region thereof.
Claim 17
Dependent Claim
36 words
A digital integrated circuit according to claim 15, wherein the digital circuit of each region comprises a shift register and wherein at least one clock signal line for all regions extends thereto over the whole wafer.
Claim 18
Dependent Claim
20 words
A digital integrated circuit according to claim 16, wherein each shift register lies wholly within the forward data flow path.
Claim 19
Dependent Claim
25 words
A digital integrated circuit according to claim 16, wherein each shift register comprises two portions lying in the forward and return data flow paths respectively.
Claim 20
Dependent Claim
94 words
A digital integrated circuit according to claim 16, wherein the shift registers of the chain of regions constitute a succession of word cells in a slow data line and wherein a fast data line extends to each word cell and is linked thereto by logical circuity adapted to compare mask addresses in command signals sent down the fast line with tag addresses in the word cells and to respond to the command signal at the word cell where a mask/tag match occurs to gate a data signal from one line into the other line.
Claim 21
Dependent Claim
21 words
A digital integrated circuit according to claim 19, wherein the shift register of each region includes a plurality of word cells.
Claim 22
Dependent Claim
37 words
A digital integrated circuit according to claim 19, including further input and output connections in parallel with the aforesaid connections and said further connections to interconnect forward and return fast line data flow paths of the regions.
Claim 23
Dependent Claim
97 words
A digital integrated circuit according to claim 21, wherein the regions are arranged in a rectangular array of rows and columns such that each region has four neighbours, the shift registers are controlled by two-phase clock signals supplied to all regions by two clock lines, the signal delay from one region to the next along the fast line being equal to half the period of each clock signal, the regions being identical and the two clock lines extending generally along the rows and/or columns but interchanging with each other in proceeding from one region to the next.
Claim 24
Dependent Claim
79 words
A digital integrated circuit according to claim 1, wherein the digital circuit of each region is a shift register and wherein the logical switching circuit of each region is normally effective to connect its shift register in a recirculating loop and to connect its input connections to its output connections directly, but is responsive to a control signal addressed thereto to break the recirculating loop and to connect its input connections to its output connections through the shift register.
Claim 25
Dependent Claim
53 words
A digital integrated circuit according to claim 1, wherein a plurality of grids of conductor lines, including two grids for the two terminals of a power supply to the regions, extend across the wafer to all regions, each grid comprising lines in two crossing directions extending to every region in both such directions.
Claim 26
Dependent Claim
35 words
A digital integrated circuit according to claim 24, wherein at least one of the grids contains fusible links for fusing in the event of a short-circuit fault to isolate a faulty chip from the grid.
References Cited (Backward Citations)
US3735368A
Cited
US3758761A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-10-13 | 1979-04-14 | 1979-10-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-10-13 | 1983-04-14 | 1983-10-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-10-13 | 1987-04-14 | 1987-10-14 | $7700.00 | Window Closed / Lapsed |