Voltage regulator circuit with relatively low power consumption

Claim 2

In combination: a charge supply circuit; means responsive to a control signal which recurs at a fixed frequency for supplying energy to said charge supply circuit during spaced time intervals which recur at said fixed frequency, said control signal having a time duration which is only a small fraction of the recurrence period of said control signal; a charge storage circuit for producing an output voltage proportional to the charge stored therein connected to said charge supply circuit for receiving charge therefrom upon the termination of each said spaced time interval; means coupled to said charge storage circuit and responsive to said control signal for sampling said output voltage across said charge storage circuit only for an interval during each recurrence period of said control signal which is not greater than the duration of said control signal; and means responsive to the sampled voltage for adjusting the duration of each said spaced time interval to a value not substantially greater than that required to permit the replacement of the charge lost by said charge storage circuit since the preceding sampling period.

Claim 3

In the combination as set forth in claim 1, said charge supply circuit comprising an inductor.

Claim 4

In the combination as set forth in claim 2, said means for supplying energy to said charge supply circuit comprising: terminals between which an operating voltage may be applied; a switch in series with said inductor, said series circuit connected between said terminals; and means for closing said switch during said spaced time intervals.

Claim 5

In the combination as set forth in claim 3, said switch comprising a transistor having base, emitter and collector electrodes, the collector electrode-to-emitter electrode path of said switch being connected in series with said inductor, and said means responsive to the sampled voltage comprising means for applying a pulse in the forward direction to the base-emitter junction of said transistor of a duration proportional to said sampled voltage.

Claim 6

In the combination as set forth in claim 1, said means responsive to the sampled voltage comprising: a two input logic gate the first of the inputs initially being at a voltage level representing one binary value and the second input initially being at a voltage level representing the other binary value; means for placing said second input at a voltage representing said one binary value during each sampling period; and means responsive to the sampled voltage for changing the value of the voltage at said first of said inputs toward the voltage representing said other binary value at a rate proportional to the value of the sampled voltage.

Claim 7

In the combination as set forth in claim 1, said means for sampling the voltage across said charge storage circuit comprising a Series circuit which includes a normally open switch responsive to said control signal connected in series with a voltage divider, said series circuit connected across said charge storage circuit, and an output terminal connected to a point along said voltage divider, whereby each time a control signal occurs said switch is closed and a voltage proportional to the voltage across said charge storage circuit appears at said output terminal.

Claim 8

In the combination as set forth in claim 1, said voltage divider comprising two resistive means, one of substantially larger value that the other, and said larger resistive means exhibiting a distributed capacitance, and further including capacitive means of larger value than said distributed capacitance, said capacitive means being connected across the resistive means of lower value.

Claim 9

In the combination as set forth in claim 6, said series circuit comprising a first adjustable resistor of relatively large value, a second resistor only a fraction of the value of said first resistor and a MOS transistor serving as said switch, said MOS transistor having a conduction path and said conduction path serving as the connection between said two resistors, said MOS transistor having a gate electrode to which said control signal is applied.

Claim 10

In the combination as set forth in claim 8, said means for sampling further including a COS/MOS inverter comprising two MOS transistors of opposite conductivity types the conduction paths of which are connected in series between the end of said voltage divider at which the resistor of lower value is located and a terminal for an operating voltage of the same polarity as the voltage across charge storage circuit, the gate electrodes of said inverter MOS transistors being connected in common to the output terminal of said voltage divider and the conduction path impedance of the inverter MOS transistor connected to said end of said voltage divider being substantially lower, when conducting, than the conduction path impedance of the other inverter MOS transistor, when conducting.

Claim 11

In a circuit which includes a voltage converter having a switch and inductor interconnected so that when the switch is closed, current passes through the inductor, and which also includes a capacitor in circuit with the inductor which is charged by the inductor when the switch opens and which also includes means for closing the switch at spaced time intervals, in combination: means, each time said switch is closed, for sampling the voltage across the capacitor for a period which is relatively very short compared to the intervals between sampling periods said means comprising a voltage divider in series with a second switch, said series circuit connected across said capacitor, and means for closing said second switch concurrently with the closing of the first mentioned switch; means responsive to the sampled voltage for producing a ramp voltage having a slope proportional to the amplitude of the sampled voltage; and means for opening the first mentioned switch when said ramp voltage reaches a predetermined threshold value.

Claim 12

In a circuit which includes a voltage converter having a switch and inductor interconnected so that when the switch is closed, current passes through the inductor, and which also includes a capacitor in circuit with the inductor which is charged by the inductor when the switch opens and which also includes means for closing the switch at spaced time intervals, in combination: means, each time said switch is closed, for sampling the voltage across the capacitor for a period which is relatively very short compared to the intervals between sampling periods said means comprising a voltage divider in series with a second switch, said series circuit connected across said capacitor, and means for closing said second switch concurrently with the closing of the first mentioned switch; means responsive to the sampled voltage for producing a ramp voltage having a slope proportional to the amplitude of the sampled voltage; and means for opening the first mentioned switch when said ramp voltage reaches a predetermined threshold value.

Claim 13

In combination: two terminals between which an operating voltage may be applied; a transistor having base, emitter and collector electrodes; an inductor connected in series with the emitter-to-collector path of said transistor between said terminals; a diode connected at one electrode to said collector electrode; a capacitor connected between the other electrode of said diode and said emitter electrode, whereby each time a turn-on pulse is applied to said base electrode, in the forward direction, current flows through said inductor and when the pulse terminates, said inductor charges said capacitor through said diode; means responsive to a recurrent control pulse which has a time duration which is only a small fraction, less than one tenth, of the recurrence period of said control pulse for sampling the voltage across said capacitor each timE a turn on pulse is applied to said base electrode and only for a period not greater than the time duration of said control pulse; means responsive to the sampled voltage for producing a signal of a duration inversely proportional to the amplitude of said voltage; and means responsive to said signal for producing said turn on pulse and applying it to said base electrode.

Claim 14

In combination: two terminals between which an operating voltage may be applied; a transistor having base, emitter and collector electrodes; an inductor connected in series with the emitter-to-collector path of said transistor between said terminals; a diode connected at one electrode to said collector electrode; a capacitor connected between the other electrode of said diode and said emitter electrode, whereby each time a turn-on pulse is applied to said base electrode, in the forward direction, current flows through said inductor and when the pulse terminates, said inductor charges said capacitor through said diode; means responsive to a recurrent control pulse which has a time duration which is only a small fraction, less than one tenth, of the recurrence period of said control pulse for sampling the voltage across said capacitor each timE a turn on pulse is applied to said base electrode and only for a period not greater than the time duration of said control pulse; means responsive to the sampled voltage for producing a signal of a duration inversely proportional to the amplitude of said voltage; and means responsive to said signal for producing said turn on pulse and applying it to said base electrode.