Method for manufacturing a semiconductor device having self-aligned implanted barriers with narrow gaps between electrodes

Claim 3

The method as recited in claim 1 wherein said electrically conducting layer formed on said first insulating layer is doped polycrystalline silicon.

Claim 4

The method as recited in claim 2 wherein said first insulating layer comprises a first layer of silicon dioxide formed on a silicon substrate and a first layer of silicon nitride formed on said layer of silicon dioxide.

Claim 5

The method as recited in claim 3 wherein said second insulating layer further comprises a second layer of silicon nitride formed on a second layer of silicon dioxide.

Claim 6

The method as recited in claim 4 wherein said silicon dioxide islands are formed by thermal oxidation of said electrically conducting layer, said second layer of silicon nitride preventing thermal oxidation except within said cavities.

Claim 7

The method as recited in claim 4 wherein said step of forming barrier regions comprises the step of irradiating ions over the surface of said structure to thereby implant ions in said substrate.

Claim 8

The method as recited in claim 6 wherein said step of selectively forming protective insulation is accomplished by the step of thermally oxidizing the surface regions of said remaining portions of said electrically conducting layer.

Claim 9

The method as recited in claim 1 wherein said step of forming a second plurality of gate electrodes comprises the step of forming a continuous conducting layer over the top surface of said structure so that portions of said conducting layer are formed on said first insulating layer in interstitial arrangement with said plurality of gate electrodes.

Claim 10

The method as recited in claim 8 wherein said step of forming a continuous conducting layer is accomplished by chemical vapor deposition.

Claim 11

The method as recited in claim 1 further comprising the step of forming a buried channel layer in the surface of said substrate.

Claim 12

A process for fabricating a self-aligned semiconductor structure having narrow gaps between associated electrodes comprising the steps of: a. forming a first oxide insulating layer on one surface of a semiconductor substrate; b. forming a first nitride insulating layer on said first oxide layer; c. forming a first conducting layer on said first nitride layer; d. forming a second layer of oxide on the surface of said first conducting layer; e. forming a second layer of nitride on said second oxide layer; f. depositing a layer of oxide on said second Nitride layer; g. forming a first layer of photoresist on said deposited oxide layer, said photoresist layer having a plurality of openings therethrough; h. removing portions of said deposited oxide layer beneath said openings in said first photoresist layer; i. forming barrier regions in said semiconductor substrate within an area defined by said openings in said deposited oxide layer and said first photoresist layer; j. removing said first photoresist layer; k. removing portions of said second nitride layer beneath openings in said deposited oxide layer; l. removing portions of said second oxide layer beneath openings in said second nitride layer; m. removing said deposited oxide layer; n. forming oxide islands on said first conducting layer within an area defined by openings in said second oxide layer; o. forming a second layer of photoresist over alternate ones of said oxide islands; p. removing said oxide islands not covered by said second photoresist layer; q. removing said second nitride layer; r. removing exposed portions of said first conducting layer within an area defined by openings in said second oxide layer; s. forming a third layer of photoresist over said second oxide layer having openings from the center of openings formed by the removal of alternate oxide islands to the center of the adjacent remaining oxide islands; t. removing portions of said second oxide layer under said openings in said third photoresist layer so as to expose the top surface of said first conducting layer; u. removing exposed portions of said first conducting layer wherein said second oxide layer, said silicon dioxide islands, and said third photoresist layer prevent removal of portions of said first conducting layer that are not exposed, thereby providing alignment between the left surface of said implanted barrier regions and respective surfaces of the remaining portions of said first conducting layer; v. removing said third photoresist layer; w. selectively forming a third oxide layer on the remaining portions of said first conducting layer, so as to provide an insulating surface; and x. forming a second conducting layer over said top insulating surface, thereby to provide a structure having barriers aligned with the corresponding edges of said remaining portions of said first conducting layer.

Claim 13

A process for fabricating a self-aligned semiconductor structure having narrow gaps between associated electrodes comprising the steps of: a. forming a first oxide insulating layer on one surface of a semiconductor substrate; b. forming a first nitride insulating layer on said first oxide layer; c. forming a first conducting layer on said first nitride layer; d. forming a second layer of oxide on the surface of said first conducting layer; e. forming a second layer of nitride on said second oxide layer; f. depositing a layer of oxide on said second Nitride layer; g. forming a first layer of photoresist on said deposited oxide layer, said photoresist layer having a plurality of openings therethrough; h. removing portions of said deposited oxide layer beneath said openings in said first photoresist layer; i. forming barrier regions in said semiconductor substrate within an area defined by said openings in said deposited oxide layer and said first photoresist layer; j. removing said first photoresist layer; k. removing portions of said second nitride layer beneath openings in said deposited oxide layer; l. removing portions of said second oxide layer beneath openings in said second nitride layer; m. removing said deposited oxide layer; n. forming oxide islands on said first conducting layer within an area defined by openings in said second oxide layer; o. forming a second layer of photoresist over alternate ones of said oxide islands; p. removing said oxide islands not covered by said second photoresist layer; q. removing said second nitride layer; r. removing exposed portions of said first conducting layer within an area defined by openings in said second oxide layer; s. forming a third layer of photoresist over said second oxide layer having openings from the center of openings formed by the removal of alternate oxide islands to the center of the adjacent remaining oxide islands; t. removing portions of said second oxide layer under said openings in said third photoresist layer so as to expose the top surface of said first conducting layer; u. removing exposed portions of said first conducting layer wherein said second oxide layer, said silicon dioxide islands, and said third photoresist layer prevent removal of portions of said first conducting layer that are not exposed, thereby providing alignment between the left surface of said implanted barrier regions and respective surfaces of the remaining portions of said first conducting layer; v. removing said third photoresist layer; w. selectively forming a third oxide layer on the remaining portions of said first conducting layer, so as to provide an insulating surface; and x. forming a second conducting layer over said top insulating surface, thereby to provide a structure having barriers aligned with the corresponding edges of said remaining portions of said first conducting layer.