Improved microprogrammed peripheral processing system

Claim 2

A data processing system comprising a central processing system, at least one storage device having predetermined operational characteristics and a peripheral processor coupled to said central processing system and to said device, said peripheral processor including hardware facilities for transferring data between said central processing system and said device in response to different types of commands specified by command bytes received from said central processing system, said processor further comprising: an addressable control memory means having a plurality of memory storage locations, at least one group of said plurality of memory storage locations for storing microinstructions of a first type of routine for directing said processor in performing control operations related to one type of said commands, said one group of said locations of said first routine storing at least one microinstruction containing a coded control byte in a predetermined one of said first group of locations and a second group of said plurality of memory storage locations storing microinstructions of a second type of routine for conditioning said processor hardware facilities for executing only those operations dependent upon said specific operational characteristics of said one peripheral device for transferring data; register storage means operatively coupled to said memory means for storing at least a control byte of information and signals representative of said command byte; and, branch control means coupled to said memory means, said branch control means being responsive to said command byte signals to cause said memory means to branch to said microinstructions of said first routine including said one type of microinstruction, said processor during execution of said first routine conditioning said storage means to store a bit representation of said control byte, said branch control means including circuit means responsive to control type microinstructions included in said second routine of microinstructions to test said control byte to determine those transfer operations to be performed by said hardware facilities for the successful execution of said one type of command.

Claim 3

The system of claim 1 wherein said addressable control memory means further includes address register means for storing a current address used to address one of said plurality of locations and increment means coupled to said address register means and wherein said branch control means further includes: return register means coupled to said address register means and to said increment means; and, branch circuit means coupled to said control memory means, said increment means and to said return register storage means, said circuit means including first gating means responsive to another type microinstruction in said first type of routine to condition said increment means to increment said current address by one and second gating means responsive to said another type of microinstruction to condition said return register means to store said incremented address and third gating means responsive to said another type of microinstruction to condition said address register means to cause said control memory means to branch to a first one of the microinstructions of said second type of routine stored in a starting location specified by said another type of microinstruction.

Claim 4

The system of claim 2 wherein said branch control means includes control means coupled to said memory address register means and to said return register means, said control means being operative at successful completion of the transfer operation performed during execution of said microinstructions of said second type of routine to refereNce said another type microinstruction stored at a next location of said second type of routine, said control means including means responsive to said another type of microinstruction for conditioning said address register means to receive the address contents of said return register means to reference additional microinstructions of said first routine for determining whether further groups of microinstructions of other second types of routines are to be executed by said processor for said successful completion of the operation specified by said one type of command.

Claim 5

The system of claim 2 wherein said another type of microinstruction is a branch microinstruction coded to include: an op code field portion coded to specify an unconditional branch operation; a branch address field portion coded to designate said starting memory location corresponding to the start of said second type routine microinstructions; a prebranch field portion coded to specify storing of a return address corresponding to said incremented current address; and, a branch to address condition field portion coded to specify selection of a memory location corresponding to said branch address field portion.

Claim 6

The system of claim 1 wherein said one peripheral device is a cyclical storage device and wherein said microinstructions of said first type of routine define one of a number of director routines for conditioning said processor in performing said control operations relating to interpreting said different types of commands for reading and writing information respectively from and to said one peripheral device and wherein said microinstructions of said second type of routine define one of two classes of execution routines for conditioning said hardware facilities as to the format of information stored, the type of transfer and the transfer rate of said one device as defined by said specific operational characteristics.

Claim 7

The system of claim 1 wherein said one microinstruction is a logic type microinstruction having at least an op code field portion and a constant field portion corresponding to said control byte coded to include a predetermined bit pattern special to said one type of command and wherein said processor includes decoder means coupled to said control memory means to generate signals in response to microinstructions read from said plurality of memory locations during execution of said routines, said decoder means being operative in response to said op code field portion of said one logic type microinstruction to generate said signals for loading a bit representation corresponding to said predetermined bit pattern into said register storage means.

Claim 8

The system of claim 6 wherein said control type microinstructions correspond to branch type microinstructions, each specifying a branch on condition based upon the state of a predetermined one of bits of said control byte and said circuit means being conditioned by said branch on condition microinstructions to determine said transfer operations required to be executed by said hardware facilities for successful completion of the operation specified by said one type of command.

Claim 9

The system of claim 6 wherein said predetermined bit pattern corresponds to a director byte having a plurality of bits coded as follows: a first bit coded to condition selectively first means in said processor hardware facilities to transfer said data between said one peripheral device and said central processing system; a second bit coded to condition selectively second means in said processor hardware facilities to ignore errors in said data information being read from said one device; third and fourth bits coded to condition selectively third means included in said processor hardware facilities during execution of one of said execution routines to return to said first type of routine upon completing processing of different predetermined portions of said data; a fifth bit coded to condition selectively fouRth means included in said hardware facilities to store signal indications for use by said processor during execution of said first routine of the status resulting from the operations performed by said hardware facilities during the performance of said second routine; and a sixth bit coded to condition selectively fifth means included in said processor hardware facilities to terminate transferring said data.

Claim 10

The system of claim 8 wherein said third bit when in a predetermined state conditions said third means during execution of said type of second routine to cause said branch control means to return control to said first type of routine after said facilities have completed processing a first one of said predetermined portions of said data and wherein said fourth bit when in a predetermined state conditions said third means during execution of said second type of routine to cause said branch control means to return control to said first type of routine when ready to begin processing a second one of said predetermined portions of said data.

Claim 11

The processor of claim 9 wherein said one peripheral device is a rotating magnetic storage unit for storing a plurality of data records along a plurality of circular tracks, each record normally having a count field portion, a key field portion and data field portion, and wherein said first one of predetermined portions of said information corresponds to a count field portion of one of said plurality of data records and said second one of said predetermined portions of said information corresponds to a data field portion of said one of said plurality of data records.

Claim 12

The processor of claim 10 wherein said one type of command is a read type of command which specifies reading said count key and data portions of one of said data records and wherein said first bit through said sixth bit of said director byte are coded initially as 101000.

Claim 13

The system of claim 10 wherein said one type of command includes a command code byte coded to condition said branch control means to have said control memory means a branch to said first type routine which selects said predetermined pattern of said director byte containing bits coded to condition said processor hardware facilities for transferring those portions of said one data record specified for said successful execution of said one type of command.

Claim 14

The system of claim 9 wherein said processor couples to a plurality of rotating, storage devices each having different media format characteristics, and wherein said processor further includes parameter storage means for storing information specifying the characteristics of a device selected to transfer said data, said addressable control memory means further including a third group of storage locations for storing at least another one of second type of microinstruction routines, each one of said second type of routines having microinstructions for conditioning said hardware facilities for executing said one type of command involving a predetermined one of said devices having different specified media format characteristics and one of said second type of routines including a control type of microinstruction, said circuit means of branch control means including means coupled to said parameter register storage means, said means being conditioned by said control type of microinstruction of said first one of said second type of routines to branch to one of said second type of routines when specified by the contents of said parameter storage means.

Claim 15

The system of claim 9 wherein said addressable control memory means includes storage locations for storage of a plurality of first and second types of routines, each of said first type of microinstruction routines coded for executing a particular type of command and including at least one microinstruction coded to contain a predetermined director byte bit pattern for indicating to an appropriate one of said second type of microinstruction routines which specific transfeR operations are to be performed for said particular type of command being executed by a designated one of said first type of microinstruction routines.

Claim 16

The system of claim 14 wherein said first type of routines includes a number of read director routines and write director routines for conditioning said processor to transfer data from said device to said central processing system and transfer data from said central processing system to said device respectively, said branch control means being conditioned by command byte signals to cause said control memory means to reference a corresponding one of said read and write director routines and wherein said second type of microinstruction routines include at least one common read execution routine and one common write execution routine operative to condition said hardware facilities to execute only those read operations and write transfer operations respectively defined by the director byte bit pattern referenced by said processor during execution of corresponding one of said director routines.

Claim 17

In a data processing system including a central processing unit and a peripheral processing system coupled to said central processing unit, said peripheral processing system including a microprogrammable input/output processor and a plurality of cyclic input/output storage devices, each having different media format characteristics, said peripheral processor having hardware facilities for executing a plurality of different types of commands received from said central processing unit for controlling the operation of said plurality of input/output storage devices during the transfer of data between said central processing unit and said devices, said processor further comprising: an addressable control store having a plurality of memory storage locations, groups of said locations storing at least two first and second classes of microprogram routines, each of said microprogram routines of said first class including at least a first type of microinstruction having an op code field and a constant field coded to include a predetermined bit pattern establishing those transfer operations to be performed during the execution of one of said types of said commands and each of said second classes of microprogram routines including microinstructions specifying transfer operations which condition said processor for execution of first and second categories of said different types of said commands involving one of said plurality of input/output storage devices having a predetermined one of said different media format characteristics; decoder means coupled to said control store, said decoder means being operative to generate control signals in response to different ones of said microinstructions read out from said control stores during execution of said routines; general register storage means for storing information required during execution of said commands and being coupled to said control store and to said decoder means; arithmetic and logic means for performing arithmetic and logic operations upon bytes applied thereto, said arithmetic and logic means being coupled to said general register means and coupled to receive a command control byte from said central processing unit coded to designate one of said plurality of different types of said commands to be executed by said processor; and, branch control means for controlling the microinstruction sequencing of said peripheral processor during execution of said routines, said branch control means being coupled to said control store and to said arithmetic and logic means, said branch control means including circuit means conditioned by signals representative of results of performing operations upon said command control byte applied from said arithmetic and logic means to branch to a corresponding one of said first classes of microprogram routines and said decoding means during the sequencing through said corresponding one of said first routines being conditioned by said op code field portion of said first type of microinstruction to generate signals for conditioning said general register storage means for storing a signal representation of said predetermined bit pattern for controlling the transfer operations performed by one of said second classes of microprogram routines selected by said processor during execution of said corresponding one of said first routines.

Claim 18

In a data processing system including a central processing unit and a peripheral processing system coupled to said central processing unit, said peripheral processing system including a microprogrammable input/output processor and a plurality of cyclic input/output storage devices, each having different media format characteristics, said peripheral processor having hardware facilities for executing a plurality of different types of commands received from said central processing unit for controlling the operation of said plurality of input/output storage devices during the transfer of data between said central processing unit and said devices, said processor further comprising: an addressable control store having a plurality of memory storage locations, groups of said locations storing at least two first and second classes of microprogram routines, each of said microprogram routines of said first class including at least a first type of microinstruction having an op code field and a constant field coded to include a predetermined bit pattern establishing those transfer operations to be performed during the execution of one of said types of said commands and each of said second classes of microprogram routines including microinstructions specifying transfer operations which condition said processor for execution of first and second categories of said different types of said commands involving one of said plurality of input/output storage devices having a predetermined one of said different media format characteristics; decoder means coupled to said control store, said decoder means being operative to generate control signals in response to different ones of said microinstructions read out from said control stores during execution of said routines; general register storage means for storing information required during execution of said commands and being coupled to said control store and to said decoder means; arithmetic and logic means for performing arithmetic and logic operations upon bytes applied thereto, said arithmetic and logic means being coupled to said general register means and coupled to receive a command control byte from said central processing unit coded to designate one of said plurality of different types of said commands to be executed by said processor; and, branch control means for controlling the microinstruction sequencing of said peripheral processor during execution of said routines, said branch control means being coupled to said control store and to said arithmetic and logic means, said branch control means including circuit means conditioned by signals representative of results of performing operations upon said command control byte applied from said arithmetic and logic means to branch to a corresponding one of said first classes of microprogram routines and said decoding means during the sequencing through said corresponding one of said first routines being conditioned by said op code field portion of said first type of microinstruction to generate signals for conditioning said general register storage means for storing a signal representation of said predetermined bit pattern for controlling the transfer operations performed by one of said second classes of microprogram routines selected by said processor during execution of said corresponding one of said first routines.

Claim 19

The processing system of claim 16 wherein said addressable control store further includes address register means for storing a current address used to address one of said plurality of locations and increment means coupled to said address register means and wherein said branch control means further includes: return register means coupled to said control store address register means and to said increment means; and, branch circuit means coupled to said control store, said increment means and to said return register storage means, said circuit means including first gating means responsive to an another type microinstruction in said first type of routine to condition said increment means to increment said current address by one and second gating means responsive to said another type of microinstruction to condition said return register means to store said incremented address and third gating means responsive to said another type of microinstruction to condition said address register means to cause said control store to branch to said first one of the microinstructions of said second type of routine stored in a starting location specified by said another type of microinstruction.

Claim 20

The system of claim 17 wherein said branch control means includes control means coupled to said control store address register means and to said return register means, said control means being operative at successful completion of the transfer operation performance during execution of said microinstructions of said second type of routine to reference said another type microinstruction stored at a next location of said second type of routine, said control means including means responsive to said another type of microinstruction for conditioning said address register means to receive the address contents of said return register means to reference additional microinstructions of said first routine for determining whether further groups of microinstructions of other second types of routines are to be executed by said processor for said successful completion of the operation specified by said one type of command.

Claim 21

The system of claim 17 wherein said another type of microinstruction is a branch microinstruction coded to include: an op code field portion coded to specify an unconditional branch operation; a branch address field portion coded to designate said starting memory location corresponding to the start of said second type routine microinstructions; a prebranch field portion coded to specify storing of a return address corresponding to said incremented current address; and, a branch to address condition field portion coded to specify selection of a memory location correspnding to said branch address field portion.

Claim 22

The system of claim 16 wherein said one microinstruction is a logic type microinstruction having at least an op code field portion and a constant field portion corresponding to said control byte coded to include a predetermined bit pattern special to said one type of command and wherein said decoder means coupled to said control store to generate signals in response to microinstructions read from said plurality of memory locations during execution of said routines and includes circuit means operative in response to said op code field portion of said one logic type microinstruction to generate said signals for loading a bit representation corresponding to said predetermined bit pattern into said register storage means.

Claim 23

The system of claim 20 wherein said control type microinstructions correspond to branch type microinstructions, each specifying a branch on condition based upon the state of a predetermined one of bits of said control byte and said circuit means being conditioned by said branch on condition microinstructions to determine said transfer operations required to be executed by said hardware facilities for successful completion of the operation specified by said one type of command.

Claim 24

The system of claim 20 wherein said predetermined bit pattern corresponds to a director byte having a plurality of bits coded as follows: a first bit coded to condition selectively first means in said processor hardware facilities to transfer said data between said one peripheral device and said central processing unit; a second bit coded to condition selectively second means in said processor hardware facilities to ignore errors in said data information being read from said one device; third and fourth bits coded to condition selectively third means included in said processor hardware facilities during execution of one of said execution routines to return to said first type of routine upon completing processing of different predetermined portions of said data; a fifth bit coded to condition selectively fourth means included in said hardware facilities to store signal indications for use by said processor during execution of said first routine of the status resulting from the operations performed by said hardware facilities during the performance of said second routine; and a sixth bit coded to condition selectively fifth means included in said processor hardware facilities to terminate transferring said data.

Claim 25

The system of claim 22 wherein said third bit when in a predetermined state conditions said third means during execution of said type of second routine to cause said branch control means to return control to said first type of routine after said facilities have completed processing a first one of said predetermined portions of said data and wherein said fourth bit when in a predetermined state conditions said third means during execution of said second type of routine to cause said branch control means to return control to said first type of routine when ready to begin processing a second one of said predetermined portions of said data.

Claim 26

The system of claim 23 wherein each of said plurality of storage devices is a rotating magnetic storage unit for storing a plurality of data records along a plurality of circular tracks, each record normally having a count field portion, a key field portion and data field portion, and wherein said first one of predetermined portions of said information corresponds to a count field portion of one of said plurality of data records and said second one of said predetermined portions of said information corresponds to a data field portion of said one of said plurality of data records.

Claim 27

The system of claim 23 wherein said addressable control store further includes storage locations for storage of a plurality of first and second types of routines, each of said first type of microinstruction routines coded for executing a particular type of command and including at least one microinstruction coded to contain a predetermined director byte bit pattern for indicating to an appropriate one of said second type of microinstruction routines which specific transfer operations are to be performed for said particular type of command being executed by a designated one of said first type of microinstruction routines.

Claim 28

The system of claim 25 wherein said first type of routines includes a number of read director routines and write director routines for conditioning said processor to transfer data from said device to said central processing system and transfer data from said central processing system to said device respectively, said branch control means being conditioned by command byte signals to cause said control memory means to reference a corresponding one of said read and write director routines and wherein said second type of mIcroinstruction routines include at least one common read execution routine and one common write execution routine operative to condition said hardware facilities to execute only those read operations and write transfer operations respectively defined by the director byte bit pattern referenced by said processor during execution of corresponding one of said director routines.