Patent US3909791A successfully refreshed from Google Patents.
US3909791A
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Selectively settable frequency divider
Assignee: International Business Machines Corp
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Filing: 1974-06-21
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Granted: 1975-09-30
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Expires: 1994-06-21
Abstract
Abstract This description is of a complete small telecommunications processor which can be set to process lines of different speed characteristics. Each of the lines is scanned in turn, and each scan is counted for each line. The line sampling can be at any selected bit rate and can be the same for some lines or can be different for each line. The frequency divider comprises a storage having a two part storage for each line, a decrementer, a register, and a feedback path back to the storage. During operation, a divisor is stored in a buffer part of storage. If the counter part of the same storage area is at zero, the buffer value is transferred through the decrementer and the register back into the counter storage. At each scan cycle thereafter, the count value is cycled and decremented until it reaches zero. This causes a pulse signal to be sent out and a reloading of the counter part with the value stored in the buffer. Continual repetition of such decrementing and reloading cycles will generate an output series of signals having a preselected frequency ratio with the input scanning frequency. If more than one line is being controlled by the frequency divider, the output signals will be interspersed in individual time slots of the output line.
Inventors
- 👤 Den Berg Jan Wouter Van
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 11:40
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/02; H04L25/0262; G; G06; G06F; G06F13/00; G06F13/10; G06F13/12; G06F13/14; G06F13/20; G06F13/22
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
264 words
A frequency dividing system for reducing a constant frequency scanner input signal by any desired integral divisor, said system comprising: a storage device having a buffer section and a counter section; a signal bus; readout means for said storage device operative during each cycle of said scanner input signal to sequentially first read out to said signal bus the data stored in said counter section and then the data stored in said buffer section; a decrementer receiving the data signals on said signal bus and operating to reduce the data represented thereby a unit value; a register settable by the output of said decrementer; register control means operative after the first operation of said readout means to set said register to the decremented value from said counter section; an overflow latch in said decrementer to generate a signal if a representation of a zero value is received from said signal bus, connections from said overflow latch to pass said signal to said register control means to render said register control means also operative after operation of said readout means to set said signal bus in accordance with the data in said buffer section to reset said regIster to the decremented value from said buffer section; a counter section control to thereafter set said counter section to the value set in said register; an input bus settable to a state to represent a divisor value; gates between said input bus and said buffer section; and gating controls to set said buffer section to a desired divisor represented by the set state of said input bus.
Claim 2
Dependent Claim
264 words
A frequency dividing system for reducing a constant frequency scanner input signal by any desired integral divisor, said system comprising: a storage device having a buffer section and a counter section; a signal bus; readout means for said storage device operative during each cycle of said scanner input signal to sequentially first read out to said signal bus the data stored in said counter section and then the data stored in said buffer section; a decrementer receiving the data signals on said signal bus and operating to reduce the data represented thereby a unit value; a register settable by the output of said decrementer; register control means operative after the first operation of said readout means to set said register to the decremented value from said counter section; an overflow latch in said decrementer to generate a signal if a representation of a zero value is received from said signal bus, connections from said overflow latch to pass said signal to said register control means to render said register control means also operative after operation of said readout means to set said signal bus in accordance with the data in said buffer section to reset said regIster to the decremented value from said buffer section; a counter section control to thereafter set said counter section to the value set in said register; an input bus settable to a state to represent a divisor value; gates between said input bus and said buffer section; and gating controls to set said buffer section to a desired divisor represented by the set state of said input bus.
Claim 3
Dependent Claim
85 words
A frequency divider as set out in claim 1, and including: a plurality of addressable buffer and counter sections in said storage device; a storage address control section to read out said addressable sections seriatim to said decrementer during one scanner cycle; a second latch settable by a value representation stored in one bit position of the addressed word of said storage device; and a pair of output signal latches alternately settable by said overflow latch and by the setting of said second settable latch.
Claim 4
Dependent Claim
77 words
A frequency divider as set out in claim 2, and including a regeneration path to return said stored value to said one bit position of said storage device; a gate deactivated by one of said output signal latches to block said recirculation path and prevent further recirculation of said stored value in said one bit position; and circuits activated by the other output signal latch when set to supply a signal for recirculation through said regeneration path.
Claim 5
Dependent Claim
198 words
A frequency reducing system settable to give an output signal after each group of a selectable integral number of input operations, said system comprising: a buffer storage settable to store a predetermined count value; a count storage section to retain a count value; a decrementer to reduce an input value by a single unit; a readout device for each said storage section; a sequence control unit; a set of control gates activated by said sequence control unit to first read out said stored count value and then said stored buffer value to the input of said decrementer for each occurrence of said input operation; a regeneration path including a settable register to hold the decremented value read out from said count section for subsequent storage in said count storage section; output circuits activated when the readout from said count storage section represents a zero value; and gates energized by said output circuits when activated to substitute the decremented value of said buffer storage readout value for the decremented count storage section value in said settable register whereby said output circuits provide a sequence of output signals at a selectable integral subharmonic of the frequency of said input operations.
Claim 6
Dependent Claim
198 words
A frequency reducing system settable to give an output signal after each group of a selectable integral number of input operations, said system comprising: a buffer storage settable to store a predetermined count value; a count storage section to retain a count value; a decrementer to reduce an input value by a single unit; a readout device for each said storage section; a sequence control unit; a set of control gates activated by said sequence control unit to first read out said stored count value and then said stored buffer value to the input of said decrementer for each occurrence of said input operation; a regeneration path including a settable register to hold the decremented value read out from said count section for subsequent storage in said count storage section; output circuits activated when the readout from said count storage section represents a zero value; and gates energized by said output circuits when activated to substitute the decremented value of said buffer storage readout value for the decremented count storage section value in said settable register whereby said output circuits provide a sequence of output signals at a selectable integral subharmonic of the frequency of said input operations.
References Cited (Backward Citations)
US3050685A
Cited
US3278727A
Cited
US3324465A
Cited
US3538442A
Cited
US3623021A
Cited
US3651414A
Cited
US3702382A
Cited
US3742195A
Cited
US3824379A
Cited
US3764790A
Cited
US3789195A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-09-29 | 1979-03-31 | 1979-09-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-09-29 | 1983-03-31 | 1983-09-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-09-29 | 1987-03-31 | 1987-09-30 | $7700.00 | Window Closed / Lapsed |