Low power gate switching device for triacs

Claim 2

A low power method for triggering an electronic semiconductor thyrister device used as a switch in a generally sinusoidal alternating current circuit comprising the steps of: a. generating two series of in-phase digital clock pulses having a period of one bit which is much shorter than the period of said alternating current and not necessarily synchronized therewith; b. clamping a sample of said alternating current to a zero reference voltage and to a low direct current voltage compatible with low power solid state digital circuitry to produce a generally trapezoidal waveform having the period of said alternating current; c. shaping said trapezoidal waveform into generally a square wave having the same period of said alternating current; d. selecting a next-in-time one bit digital clock pulse each time said square wave has gone through a voltage amplitude transition; e. delaying said one bit digital clock pulse until said alternating current has passed through a zero voltage reference point and is of sufficient voltage amplitude to sustain said thyrister device in a conduction mode; and f. applying said delayed one bit digital clock pulse to a control gate of said thyrister device whereby said device is triggered into self sustaining coNduction.

Claim 3

The method of claim 1 additionally comprising the step of amplifying said delayed one bit digital control pulse to match the forward breakover voltage characteristic of said thyrister device so as to trigger it into self sustaining conduction.

Claim 4

The method of claim 2 wherein said two series of in-phase digital clock pulses have a one bit period of approximately 100 microseconds and said alternating current has a frequency of generally 60 hertz.

Claim 5

The method of claim 3 wherein said one bit digital clock pulse is delayed for a minimum of one bit incident to a transition of said square wave from the zero reference voltage to the low direct current voltage and is delayed for a minimum of three bits incident to a transition of said square wave from the low direct current voltage to the zero reference voltage.

Claim 6

The method of claim 4 comprising the additional step of further delaying said one bit digital clock pulse for a predetermined fractional amount of the period of said alternating current, said fraction always being no greater than one half, whereby the duty cycle of said thyrister device may be regulated.

Claim 7

The method of claim 4 for triggering a triac.

Claim 8

The method of claim 5 for triggering a triac.

Claim 9

A low power solid state clocked digital control circuit for triggering an electronic semiconductor thyrister device used as a switch in a generally sinusoidal alternating current circuit comprising: a. a clamp circuit connected to said alternating current and adapted to limit a sample thereof between a zero reference voltage and a low direct current voltage compatible with said clamp circuit, the output thereof resulting in a generally trapezoidal waveform having the period of said alternating current; b. waveform shaping circuit means connected to said clamp circuit for shaping said trapezoidal waveform into generally a square wave having the same period of said alternating current; c. digital clock means connected to said control circuit and generating clock pulses having a period of one bit which is shorter than the period of said alternating current and not necessarily synchronized therewith; d. a detector circuit connected to said clock and to the output of said waveform shaping circuit and adapted to select a next-in-time one bit clock pulse each time said square wave has gone through a voltage amplitude transition; e. storage circuitry connected to said detector circuit and said clock means and adapted to delay said one bit pulse until said alternating current has passed through a zero voltage reference point and is of sufficient voltage amplitude to sustain said thyrister device in a conduction mode; f. a gate on said thyrister device connected to said storage circuitry to receive said delayed one bit pulse.

Claim 10

A low power solid state clocked digital control circuit for triggering an electronic semiconductor thyrister device used as a switch in a generally sinusoidal alternating current circuit comprising: a. a clamp circuit connected to said alternating current and adapted to limit a sample thereof between a zero reference voltage and a low direct current voltage compatible with said clamp circuit, the output thereof resulting in a generally trapezoidal waveform having the period of said alternating current; b. waveform shaping circuit means connected to said clamp circuit for shaping said trapezoidal waveform into generally a square wave having the same period of said alternating current; c. digital clock means connected to said control circuit and generating clock pulses having a period of one bit which is shorter than the period of said alternating current and not necessarily synchronized therewith; d. a detector circuit connected to said clock and to the output of said waveform shaping circuit and adapted to select a next-in-time one bit clock pulse each time said square wave has gone through a voltage amplitude transition; e. storage circuitry connected to said detector circuit and said clock means and adapted to delay said one bit pulse until said alternating current has passed through a zero voltage reference point and is of sufficient voltage amplitude to sustain said thyrister device in a conduction mode; f. a gate on said thyrister device connected to said storage circuitry to receive said delayed one bit pulse.

Claim 11

The circuitry of claim 8 additionally comprising an amplifier circuit connected between said storage circuitry and said thyrister device gate and adapted to increase the amplitude of said one bit pulse to match the forward breakover characteristic of said one bit pulse to trigger said thyrister device into self sustaining conduction.

Claim 12

The circuitry of claim 8 adapted for a 60 hertz alternating current and wherein the clock means generates clock pulses at a frequency of approximately 10 kilohertz.

Claim 13

The circuitry of claim 9 additionally comprising a digitally controlled delay circuit interconnected with said storage circuitry and adapted to further delay said one bit pulse for a predetermined fractional amount of the period of said alternating current, said fraction always being no greater than one half, whereby the duty cycle of said thyrister device may be regulated.

Claim 14

The control circuit of claim 11 wherein said circuitry is implemented with large scale integrated two phase dynamic MOS semiconductor devices and said clock means generates two series of in-phase clock pulses with each series having a different average power and the same period, and Said trapezoidal waveform shaping means is a Schmidt circuit, and said storage circuitry and delay circuit are made up of a predetermined number of interconnected controlled two phase one bit MOS shift registers.

Claim 15

The control circuit of claim 11 adapted for use with a triac.

Claim 16

In a two phase dynamic p-channel MOS large scale integrated semiconductor device, a low power clocked digital gate control circuit for triggering the self conduction of a triac used as a switch in a generally 60 hertz sinusoidal alternating current circuit comprising: a clamp circuit connected to said alternating current and having an output in the form of a trapezoid of the period of said alternating current and an amplitude generally from zero reference point being a zero state to a fixed predetermined minus being a one state; a Schmidt circuit connected to the output of said clamp circuit and adapted to convert said trapezoidal waveform into a generally square wave; a clock pulse source having an output of two phase in time digital clock pulses of a period of generally 100 microseconds, said period being equivalent to one bit; a first one bit delay circuit connected to the output of said Schmidt circuit and to said clock pulse source whereby the said square wave is delayed in time for the period of one bit; a digital inverter connected to the output of said one bit delay circuit and adapted to invert said square wave; a first one-to-zero transition detector connected to the output of said inverter and to said clock source and adapted to output a one bit trigger pulse when a one to zero transition occurs in said inverted square wave; a digital logic ''''or'''' gate circuit having one of two inputs connected to the output of said first one-to-zero transition detector and having an output; a digital logic ''''and'''' gate circuit having one of two inputs connected to the output of said ''''or'''' gate and having an output; a digital control latch circuit connected to the second input of said ''''and'''' gate and to external digital control circuitry and adapted to pass clock pulses when triac triggering is intended; an amplifier connected between the output of said ''''and'''' gate and the gate of said triac and adapted to amplify said trigger pulse to a sufficient amplitude to trigger said triac into self sustaining conduction; a second one-to-zero transition detector connected to the output of said first one bit delay circuit and to said clock source and adapted to output a one bit trigger pulse when a one-to-zero transition occurs in said square wave; a second one bit delay circuit connected to the output of said second one-to-zero transition detector and to said clock source and adapted to delay the output pulse from said second detector by a period of one bit; and a third one bit delay circuit connected to the output of said second one bit delay circuit and to said clock source and adapted to delay said delayed pulse from said second delay circuit by a period of one bit and having an output connected to the second input of said ''''or'''' gate.

Claim 17

In a two phase dynamic p-channel MOS large scale integrated semiconductor device, a low power clocked digital gate control circuit for triggering the self conduction of a triac used as a switch in a generally 60 hertz sinusoidal alternating current circuit comprising: a clamp circuit connected to said alternating current and having an output in the form of a trapezoid of the period of said alternating current and an amplitude generally from zero reference point being a zero state to a fixed predetermined minus being a one state; a Schmidt circuit connected to the output of said clamp circuit and adapted to convert said trapezoidal waveform into a generally square wave; a clock pulse source having an output of two phase in time digital clock pulses of a period of generally 100 microseconds, said period being equivalent to one bit; a first one bit delay circuit connected to the output of said Schmidt circuit and to said clock pulse source whereby the said square wave is delayed in time for the period of one bit; a digital inverter connected to the output of said one bit delay circuit and adapted to invert said square wave; a first one-to-zero transition detector connected to the output of said inverter and to said clock source and adapted to output a one bit trigger pulse when a one to zero transition occurs in said inverted square wave; a digital logic ''''or'''' gate circuit having one of two inputs connected to the output of said first one-to-zero transition detector and having an output; a digital logic ''''and'''' gate circuit having one of two inputs connected to the output of said ''''or'''' gate and having an output; a digital control latch circuit connected to the second input of said ''''and'''' gate and to external digital control circuitry and adapted to pass clock pulses when triac triggering is intended; an amplifier connected between the output of said ''''and'''' gate and the gate of said triac and adapted to amplify said trigger pulse to a sufficient amplitude to trigger said triac into self sustaining conduction; a second one-to-zero transition detector connected to the output of said first one bit delay circuit and to said clock source and adapted to output a one bit trigger pulse when a one-to-zero transition occurs in said square wave; a second one bit delay circuit connected to the output of said second one-to-zero transition detector and to said clock source and adapted to delay the output pulse from said second detector by a period of one bit; and a third one bit delay circuit connected to the output of said second one bit delay circuit and to said clock source and adapted to delay said delayed pulse from said second delay circuit by a period of one bit and having an output connected to the second input of said ''''or'''' gate.

Claim 18

The circuit of claim 13 additionally comprising a programmable series of shift register circuits connected to the clock source and to said control circuit and adapted to delay said trigger pulses for a variable predetermined fraction of the period of said 60 hertz alternating current, whereby the duty cycle of said triac may be controlled.