US3909562A — Switching network testing process and arrangement

Claim 1

Independent Claim 315 words

A testing process to test the operation of a multistage time-division switching network by compariNg a sample transmitted through said switching network with said sample prior to said transmission comprising the steps of: storing an address of an outgoing time-division switch transmitting said sample from an ingoing time-division channel for each new connection established via said ingoing channel, said address including an input address of said ingoing channel of an ingoing time-division switch that receives said ingoing channel and a switch address of said ingoing switch; generating said switch address; storing a duplicate of said sample applied to data inputs of a speech memory in said ingoing switch having its address generated when a write address identical to said generated switch address is applied to inputs of said speech memory; detecting the occurrence of a read address identical to said generated switch address at addressing inputs of said speech memory in said ingoing switch having its switch address generated; delaying by a predetermined period following completion of said detecting step; storing a write address from a time-division address memory in said selected outgoing switch, said write address being provided from a special memory as a function of said generated switch address; said predetermined period being as long as the time of transmitting said sample through a space-division switch of said network; detecting the occurrence of a read address identical to said write address stored in said last mentioned storing step at addressing inputs of a speech memory of said selected outgoing switch; deriving a duplicate of said sample at the output of said speech memory of said selected outgoing switch when said last mentioned detecting step is completed; comparing said sample stored in the second above-mentioned storing step with said sample derived in said above-mentioned deriving step; and transmitting the results of said comparing step to appropriate circuits for initiating said process on another sample.

Claim 2

Dependent Claim 315 words

A testing process to test the operation of a multistage time-division switching network by compariNg a sample transmitted through said switching network with said sample prior to said transmission comprising the steps of: storing an address of an outgoing time-division switch transmitting said sample from an ingoing time-division channel for each new connection established via said ingoing channel, said address including an input address of said ingoing channel of an ingoing time-division switch that receives said ingoing channel and a switch address of said ingoing switch; generating said switch address; storing a duplicate of said sample applied to data inputs of a speech memory in said ingoing switch having its address generated when a write address identical to said generated switch address is applied to inputs of said speech memory; detecting the occurrence of a read address identical to said generated switch address at addressing inputs of said speech memory in said ingoing switch having its switch address generated; delaying by a predetermined period following completion of said detecting step; storing a write address from a time-division address memory in said selected outgoing switch, said write address being provided from a special memory as a function of said generated switch address; said predetermined period being as long as the time of transmitting said sample through a space-division switch of said network; detecting the occurrence of a read address identical to said write address stored in said last mentioned storing step at addressing inputs of a speech memory of said selected outgoing switch; deriving a duplicate of said sample at the output of said speech memory of said selected outgoing switch when said last mentioned detecting step is completed; comparing said sample stored in the second above-mentioned storing step with said sample derived in said above-mentioned deriving step; and transmitting the results of said comparing step to appropriate circuits for initiating said process on another sample.

Claim 3

Dependent Claim 310 words

A testing arrangement for a multistage time-division switching network comprising: a switching network control computer assembly; a control addressing means coupled to said assembly capable of providing for each control operation a binary input address of a sample from which a duplicate sample is derived for comparison purposes; first storage means coupled to said assembly to store in a special memory row an address of an outgoing time-division switch which is selected for transmitting said sample as soon as said address of said outgoing switch is provided from said assembly when establishing a communication connection involving said sample, said special memory row having said address of said sample input address; second storage means coupled to said control addressing means to store for the duration of a control operation a duplicate of said sample stored in an ingoing speech memory of an ingoing time-division switch addressed by said control addressing means at a time-division address identical to the address provided by said control addressing means; means for determining coupled to said outgoing switch, said determining means determining a time-division address of said sample in an outgoing speech memory of said outgoing switch transmitting said sample, said determining means being rendered operative after a predetermined period following a read addressing of an ingoing speech memory processing said sample so as to store for the remaining time of a particular control operation a time-division address memory of said outgoing switch transmitting said sample; comparison means coupled to said first and second storage means to compare said samples stored therein when the time-division address stored in said determining means is identical to the address provided from a clock; and translating means coupled to said comparison means and said control addressing means to increment said control addressing means in response to the output signal of said comparison means at the End of each control operation.

Claim 4

Dependent Claim 310 words

A testing arrangement for a multistage time-division switching network comprising: a switching network control computer assembly; a control addressing means coupled to said assembly capable of providing for each control operation a binary input address of a sample from which a duplicate sample is derived for comparison purposes; first storage means coupled to said assembly to store in a special memory row an address of an outgoing time-division switch which is selected for transmitting said sample as soon as said address of said outgoing switch is provided from said assembly when establishing a communication connection involving said sample, said special memory row having said address of said sample input address; second storage means coupled to said control addressing means to store for the duration of a control operation a duplicate of said sample stored in an ingoing speech memory of an ingoing time-division switch addressed by said control addressing means at a time-division address identical to the address provided by said control addressing means; means for determining coupled to said outgoing switch, said determining means determining a time-division address of said sample in an outgoing speech memory of said outgoing switch transmitting said sample, said determining means being rendered operative after a predetermined period following a read addressing of an ingoing speech memory processing said sample so as to store for the remaining time of a particular control operation a time-division address memory of said outgoing switch transmitting said sample; comparison means coupled to said first and second storage means to compare said samples stored therein when the time-division address stored in said determining means is identical to the address provided from a clock; and translating means coupled to said comparison means and said control addressing means to increment said control addressing means in response to the output signal of said comparison means at the End of each control operation.

Claim 5

Dependent Claim 81 words

An arrangement according to claim 2, wherein said control addressing means includes a binary counter coupled to said assembly and said translation means providing each of the different possible sample input addresses in said network, said counter being presettable by said assembly so as to deliver a predetermined input address and to be incremented step by step by said translation means at the end of each control operation so as to deliver for the next control operation an appropriate input address.

Claim 6

Dependent Claim 83 words

An arrangement according to claim 3, wherein said first storage means includes a memory coupled to said assembly and said control addressing means having as many rows as ingoing time-division channels in said network, each of said rows having a different input address which in write operation is delivered by said assembly and in read operation is delivered by said control addressing means, each of said rows being capable of storing the address of said outgoing switch which is supplied by said assembly.

Claim 7

Dependent Claim 261 words

An arrangement according to claim 4, wherein said second storage means includes a first multiplexer coupled to said counter and ingoing updating circuits in said ingoing time-division switches, said first multiplexer being addressed by said counter output assigned to an address of said ingoing switch involved in a test operation and having data inputs from a selected one of said ingoing updating circuits so as to allow transmission of a time-division address from said ingoing switch addressed by said counter for said test operation, a second multiplexer coupled to said counter and input circuits of said ingoing switches, said second multiplexer being addressed by said counter output assigned to an address of said ingoing switch involved in a test operation and having data inputs from a selected one of said input circuits in parallel with an associated one of said ingoing speech memories so as to allow transmission of said sample only from said selected one of said input circuits addressed by said counter for said test operation, a first comparator coupled to outputs of said counter assigned to the time-division address of said sample concerned with said test operation and to the output of said first multiplexer so as to deliver a specific signal when detecting an address from said first multiplexer identical to an address delivered by said counter, and a first storage register coupled to said first comparator and said second multiplexer activated by said specific signal so as to store for the duration of said test operation said sample transmitted by said second multiplexer when it occurs.

Claim 8

Dependent Claim 73 words

An arrangement according to claim 5, wherein said determining means includes a first arrangement coupled to said ingoing switches, said counter and said storage register for determining the read time of said sample from said ingoing speech memory, a second arrangement coupled to said memory and said outgoing switches for determining the read time of said sample from said outgoing speech memory, and a timing circuit coupled between said first and second arrangements.

Claim 9

Dependent Claim 137 words

An arrangement according to claim 6, wherein said first arrangement includes a third multiplexer coupled to said counter and a time-division ingoing address memory in each of said ingoing switches, said third multiplexer being addressed by said counter output assigned to an address of said ingoing switch involved in said test operation and having data inputs connected to said ingoing address memories so as to allow transmission of only that address from said ingoing address memory addressed by said counter for said test operation, and a second comparator coupled to said third multiplexer and to the outputs of said counter assigned to the time-division address of said sample involved in said test operation so as to deliver a specific transmission signal when detecting an address from said third multiplexer identical to aN address delivered by said counter.

Claim 10

Dependent Claim 34 words

An arrangement according to claim 7, wherein said timing circuit delays said specific transmission signal by a time delay equal to the transmission time of said sample through a space-division switch of said network.

Claim 11

Dependent Claim 143 words

An arrangement according to claim 8, wherein said second arrangement includes a fourth multiplexer coupled to said memory, said outgoing switches and said timing circuit, said fourth multiplexer being addressed by said memory, activated by said specific transmission signal and having data inputs coupled to a time-division address memory of said outgoing switch involved in said test operation to deliver the time-division address of said sample at the time of arrival of said sample in said involved outgoing switch, a second storage register coupled to said fourth multiplexer to store said time-division address delivered by said fourth multiplexer, and a third comparator coupled to the output of said second register and to addressing outputs of a network clock so as to deliver a predetermined signal when detecting a time-division address from said second register identical to a time-division address from said network clock.

Claim 12

Dependent Claim 128 words

An arrangement according to claim 9, wherein said comparison means includes a fifth multiplexer coupled to said memory said third comparator and said outgoing switches, said fifth multiplexer being addressed by said memory, activated by said predetermined signal and having data inputs coupled to said outgoing speech memories connected in parallel to time-division output circuits of said outgoing switches so as to allow transmission of said samples from said outgoing memory addressed by said memory for said test operation when said fifth multiplexer is operative, and a fourth comparator coupled to said first storage register and to said fifth multiplexer to provide at least a fault detection signal in the case of a difference between said samples present in said first storage register and in said fifth multiplexer.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1978-09-29	1979-03-31	1979-09-30	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1982-09-29	1983-03-31	1983-09-30	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	1986-09-29	1987-03-31	1987-09-30	$7700.00	Window Closed / Lapsed

Switching network testing process and arrangement

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