Path testing device for time channel connection network

Claim 2

A path testing device for a time division switching system including a central computer and a time division switching network with stages made up of an input stage, an intermediate stage, and an output stage, said input stage including n input time switches with n inputs and at most 2n-1 outputs, said intermediate stage including at most 2n-1 intermediate time switches with n inputs and n outputs, and said output stage including n output time switches having at most 2n-1 inputs and n outputs, each input time switch and each output time switch being linked by an intermediate network line to all of the intermediate time switches, each time switch having a similar internal structure which includes a buffer memory and a command memory, said path testing device comprising: a central occupation state memory containing a number of words corresponding to the total number of intermediate network lines, each word containing as many bits as there are time channels in an intermediate network line; decision and command logic control means, permanently connected to said computer for sequentially arranging and commanding the various elements of said device; selection switches address register means, responsive to said decision and command logic control means, for selectively storing the addresses of input, intermediate and output time switches; address decoder means, coupled to said selection switches address register means, for accessing said central occupation state memory; a reading/writing register, coupled to said central memory, for selectively reading or writing a memory word out of or into said central memory; a free time channel selection circuit coupled to the output of said reading/writing register; a time channel number register for storing the number of the time channel tO be entered or erased in said central occupation state memory; a decimal/binary decoder coupled between said time channel selection circuit and the input of said time channel register; and a binary/decimal decoder coupled between the output of the time channel register and said central occupation state memory; wherein the elements of the path testing device are so interconnected as to enable the device to conduct a path test prior to the establishment of a communication between an input time switch and an output time switch, but also for a path release at the end of a communication, said device including said central occupation state memory containing at any movement the occupation state of the intermediate network lines and their time channels for the entire time division switching network.

Claim 3

A device according to claim 1 wherein said decision and command logic control means includes; an information reception register coupled to said central computer for receiving information from said computer, an information transmission register coupled to said central computer for transmitting information to said central computer, and a sequential command circuit for translating and supervising the execution of commands from said central computer to the different elements of the said device and for transmitting to said central computer the occupation states of said device.

Claim 4

A device according to claim 1 wherein said reading/writing register comprises 32 flip-flops and 32 OR gates, the input of each of said flip-flops being coupled to a different output of a different one of said OR gates, said OR gates including two inputs each, one input of each of said OR gates being coupled to said central memory, the other input of each of said OR gates being coupled to said binary/decimal decoder coupled to the output of said time channel register, the outputs of said reading/writing register being coupled to the inputs of said selection circuit and to said central memory such that in a path test said selection circuit selects a free time channel and its designation as such consecutively entered into the central memory.

Claim 5

A device according to claim 3 wherein said address register means includes an intermediate time switch address register, an input/output time switch address register, and a register for storing an indication of whether an input network line time channel or an output network line time channel is being selected, a first binary/decimal decoder coupled to said intermediate time switch address register and a second binary/decimal decoder coupled to said input/output time switch address register.

Claim 6

A device according to claim 4 wherein each word stored within said central memory is a 32 bit word, and said central memory has associated therewith a three input AND gate, a first input of each of said AND gates being coupled to said first binary/decimal decoder, a second input of each of said AND gates being coupled to said second binary/decimal decoder and the third input of each of said AND gates being coupled to said register corresponding to the time channel being selected, wherein the energization of the three inputs of an AND gate determines a particular single word in said memory.

Claim 7

A device according to claim 5 wherein said selection circuit includes 32 inputs coupled to 32 outputs of said reading/writing register and 32 outputs corresponding to the 32 time channels of a network line for indicating the existence of a free time channel and further including a 33 output line for indicating that there are no free channels, said selection circuit comprising 31 AND gates and 32 inverters, said AND gates and inverters being coupled in cascade.

Claim 8

In a path testing device for a time division switching system including a central computer and a time division switching network with stages made up of an input stage, an intermediate stage, and an output stage, said input staGe including n input time switches with n inputs and most 2n-1 outputs, said intermediate stage including at most 2n-1 intermediate time switches with n inputs and n outputs, said output stage including n output time switches having at most 2n-1 inputs and n outputs, each input time switch and each output time switch being linked by an intermediate network line to all of the intermediate time switches, each time switch having a similar internal structure which includes a buffer memory and a command memory, said path test device comprising a central occupation state memory containing a number of words corresponding to the total number of intermediate network lines, each word containing as many bits as there are time channels in an intermediate network line; decision and command logic control means, permanently connected to said computer for sequentially arranging and commanding the various elements of said device; selection switches address register means, responsive to said decision and command logic control means, for selectively storing the addresses of input, intermediate and output time switches; address decoder means, coupled to said selection switches address register means for accessing said central occupation state memory; a reading/writing register, coupled to said central memory, for selectively reading or writing a memory word out of or into said central memory; a free time channel selection circuit coupled to the output of said reading/writing register; a time channel number register for storing the number of the time channel to be entered or erased in said central occupation stage memory; a decimal/binary decoder coupled between said time channel selection circuit and the input of said time channel register; and a binary/decimal decoder coupled between the output of the time channel register and said central occupation state memory; a method for testing for and selecting a path between an input and an output of said intermediate stage, in response to a path test command giving the number of one incoming intermediate network line and the number of one outgoing intermediate network line, comprising the steps of: determining an intermediate time switch having a free time channel on an incoming intermediate network line; storing the number of said intermediate time switch; determining the existence of a free time channel on said outgoing intermediate network line; and writing in said central memory at the location corresponding to the selected incoming and outgoing time channels of each intermediate network line an indication that they are no longer free, said step of writing being carried out prior to the informing of said central computer that a positive path test has been accomplished.

Claim 9

In a path testing device for a time division switching system including a central computer and a time division switching network with stages made up of an input stage, an intermediate stage, and an output stage, said input staGe including n input time switches with n inputs and most 2n-1 outputs, said intermediate stage including at most 2n-1 intermediate time switches with n inputs and n outputs, said output stage including n output time switches having at most 2n-1 inputs and n outputs, each input time switch and each output time switch being linked by an intermediate network line to all of the intermediate time switches, each time switch having a similar internal structure which includes a buffer memory and a command memory, said path test device comprising a central occupation state memory containing a number of words corresponding to the total number of intermediate network lines, each word containing as many bits as there are time channels in an intermediate network line; decision and command logic control means, permanently connected to said computer for sequentially arranging and commanding the various elements of said device; selection switches address register means, responsive to said decision and command logic control means, for selectively storing the addresses of input, intermediate and output time switches; address decoder means, coupled to said selection switches address register means for accessing said central occupation state memory; a reading/writing register, coupled to said central memory, for selectively reading or writing a memory word out of or into said central memory; a free time channel selection circuit coupled to the output of said reading/writing register; a time channel number register for storing the number of the time channel to be entered or erased in said central occupation stage memory; a decimal/binary decoder coupled between said time channel selection circuit and the input of said time channel register; and a binary/decimal decoder coupled between the output of the time channel register and said central occupation state memory; a method for testing for and selecting a path between an input and an output of said intermediate stage, in response to a path test command giving the number of one incoming intermediate network line and the number of one outgoing intermediate network line, comprising the steps of: determining an intermediate time switch having a free time channel on an incoming intermediate network line; storing the number of said intermediate time switch; determining the existence of a free time channel on said outgoing intermediate network line; and writing in said central memory at the location corresponding to the selected incoming and outgoing time channels of each intermediate network line an indication that they are no longer free, said step of writing being carried out prior to the informing of said central computer that a positive path test has been accomplished.

Claim 10

A method according to claim 7, further including a series of steps for releasing a path through said intermediate stage, in response to a path release command, comprising the steps of: reading the location in the central memory corresponding to the intermediate outgoing network line time channel which is to be released; transferring the contents of that memory location into said time channel register; erasing the contents of said memory location, so as to indicate the free status of the time channel; rewriting a new word indicating the free status of said channel into the memory at the location corresponding to the time channel which has been freed; reading the storage location corresponding to the intermediate input network line time channel; transferring the contents of said memory location into said time channel register; erasing the contents of said memory location, so as to indicate the free status of said intermediate input network time channel; and writing a new word indicating the free status of the time channel into the memory location of the central memory corresponding to the time channel of thE intermediate input network line.