Data coding circuits for encoded waveform with constrained charge accumulation

Claim 2

An encoder for encoding a data bit as a pair of code bits according to a (5,3) indirect code, comprising, means providing a data bit to be encoded and the next two data bits, means responsive to said data bit to be encoded, to said next two data bits, to two bits for identifying the existing state of the encoding operation, and to the preceding pair of code bits for producing a next pair of code bits and the next two bits identifying the resulting encoding state, and means responsive to said pair of code bits and to said next bits for identifying the resulting encoding state to form said bits identifying the state of the encoding operation and said preceding code bits for encoding the next of said data bits.

Claim 3

The encoder of claim 1 wherein said means for producing said pair of code bits further includes means producing an error signal identifying invalid combinations of said data bits and state identifying bits.

Claim 4

The encoder of claim 2 wherein said means for producing said code bits, said state identifying bits and said error signal comprises a logic array constructed according to Table 17.

Claim 5

A decoder for a (5,3) indirect code, in which a code bit pair represents a data bit comprising, means for providing code bit pairs for a bit to be decoded, the two preceding data bits, and the next two data bits, logic means for decoding said bit to be decoded according to said code bit pairs, and means connecting said logic means to receive said code bit pairs.

Claim 6

A decoder for a (5,3) indirect code, in which a code bit pair represents a data bit comprising, means for providing code bit pairs for a bit to be decoded, the two preceding data bits, and the next two data bits, logic means for decoding said bit to be decoded according to said code bit pairs, and means connecting said logic means to receive said code bit pairs.

Claim 7

A decoder for a (4,3) indirect code in which a code bit pair represents a data bit, comprising, means for storing a three bit signal identifying the existing state of the decoding operation, means providing a code bit pair for the data bit to be decoded, and logic means for decoding said bit to be decoded according to said code bits and said three bits identifying the encoding state and for producing three code bits defining the resulting state of the encoding operation.

Claim 8

A decoder for a (4,3) indirect code in which a code bit pair represents a data bit, comprising, means for storing a three bit signal identifying the existing state of the decoding operation, means providing a code bit pair for the data bit to be decoded, and logic means for decoding said bit to be decoded according to said code bits and said three bits identifying the encoding state and for producing three code bits defining the resulting state of the encoding operation.

Claim 9

A zero modulation encoder, comprising, means providing a data bit to be encoded and a plurality of adjacent data bits, said bits appearing as any one of 2n 1 combinations, where n is the number of adjacent bits, a plurality of logic means each connected to receive the data bit to be encoded, the adjacent data bits, and a signal for identifying the existing state of the encoding operation, and each having means for producing a code bit pair and a signal for identifying the resulting state of the encoding operation, said plurality of logic means including, first logic means operable in a first encoding state for encoding a data bit in a first binary fraction of said combinations as a code bit pair and producing a signal for identifying a second coding state, second logic means operable in said first encoding state for encoding a data bit in a second binary fraction of said combinations as a different code bit pair and producing a signal for identifying a third coding state, third logic means operable in said first encoding state for encoding a data bit in a remaining binary fraction of said combinations as a code bit pair and producing a signal for identifying a fourth coding state and additional logic means operable in other enCoding states for encoding a data bit of a binary fraction of said combinations as a code bit pair and producing a signal for identifying a next coding state for operating in an (R, C) code, where R is a run length in the range 4- 6 and C is a charge constraint equal to 3.

Claim 10

A zero modulation encoder, comprising, means providing a data bit to be encoded and a plurality of adjacent data bits, said bits appearing as any one of 2n 1 combinations, where n is the number of adjacent bits, a plurality of logic means each connected to receive the data bit to be encoded, the adjacent data bits, and a signal for identifying the existing state of the encoding operation, and each having means for producing a code bit pair and a signal for identifying the resulting state of the encoding operation, said plurality of logic means including, first logic means operable in a first encoding state for encoding a data bit in a first binary fraction of said combinations as a code bit pair and producing a signal for identifying a second coding state, second logic means operable in said first encoding state for encoding a data bit in a second binary fraction of said combinations as a different code bit pair and producing a signal for identifying a third coding state, third logic means operable in said first encoding state for encoding a data bit in a remaining binary fraction of said combinations as a code bit pair and producing a signal for identifying a fourth coding state and additional logic means operable in other enCoding states for encoding a data bit of a binary fraction of said combinations as a code bit pair and producing a signal for identifying a next coding state for operating in an (R, C) code, where R is a run length in the range 4- 6 and C is a charge constraint equal to 3.

Claim 11

A zero modulation encoder, comprising, means providing a data bit to be encoded and the next two adjacent data bits, said bits appearing as any one of eight combinations, a plurality of logic means each connected to receive the data bit to be encoded, the adjacent data bits, and a signal for identifying the existing state of the encoding operation, and each having means for producing a code bit pair and a signal for identifying the resulting state of the encoding operation, said plurality of logic means including, first logic means operable in a first encoding state for encoding a data bit in a first binary fraction of said combinations as a code bit pair and producing a signal for identifying a second coding state, second logic means operable in said first encoding state for encoding a data bit in a second binary fraction of said combinations as a different code bit pair and producing a signal for identifying a third coding state, third logic means operable in said first encoding state for encoding a data bit in a remaining binary fraction of said combinations as a code bit pair and producing a signal for identifying a fourth coding state, and additional logic means for providing eight encoding states for operating in a (4,3) code.

Claim 12

A zero modulation encoder, comprising, means providing a data bit to be encoded and the next two adjacent data bits, said bits appearing as any one of eight combinations, a plurality of logic means each connected to receive the data bit to be encoded, the adjacent data bits, and a signal for identifying the existing state of the encoding operation, and each having means for producing a code bit pair and a signal for identifying the resulting state of the encoding operation, said plurality of logic means including, first logic means operable in a first encoding state for encoding a data bit in a first binary fraction of said combinations as a code bit pair and producing a signal for identifying a second coding state, second logic means operable in said first encoding state for encoding a data bit in a second binary fraction of said combinations as a different code bit pair and producing a signal for identifying a third coding state, third logic means operable in said first encoding state for encoding a data bit in a remaining binary fraction of said combinations as a code bit pair and producing a signal for identifying a fourth coding state, and additional logic means for providing eight encoding states for operating in a (4,3) code.

Claim 13

The zero modulation encoder of claim 7 wherein each of said means for providing a signal for identifying the resulting encoding state comprises means for providing a three bit code.

Claim 14

A zero modulation encoder, comprising, means providing a data bit to be encoded and the next two adjacent data bits, said bits appearing as any one eight combinations, a plurality of logic means each connected to receive the data bit to be encoded, the adjacent data bits, and a signal for identifying the existing state of the encoding operation, and each having means for producing a code bit pair and a signal for identifying the resulting state of the encoding operation, said plurality of logic means including, first logic means operable in a first encoding state for encoding a data bit in a first binary fraction of said combinations as a code bit pair and producing a signal for identifying a second coding state, second logic means operable in said first encoding state for encoding a data bit in a second binary fraction of said combinations as a different code bit pair and producing a signal for identifying a third coding state, third logic means operable in said first encoding state for encoding a data bit in a remaining binary fraction of said combinations as a code bit pair and producing a signal for identifying a fourth coding state, and additional logic means for providing at least nine encoding states for operating in a (4,3) code.

Claim 15

A zero modulation encoder, comprising, means providing a data bit to be encoded and the next two adjacent data bits, said bits appearing as any one eight combinations, a plurality of logic means each connected to receive the data bit to be encoded, the adjacent data bits, and a signal for identifying the existing state of the encoding operation, and each having means for producing a code bit pair and a signal for identifying the resulting state of the encoding operation, said plurality of logic means including, first logic means operable in a first encoding state for encoding a data bit in a first binary fraction of said combinations as a code bit pair and producing a signal for identifying a second coding state, second logic means operable in said first encoding state for encoding a data bit in a second binary fraction of said combinations as a different code bit pair and producing a signal for identifying a third coding state, third logic means operable in said first encoding state for encoding a data bit in a remaining binary fraction of said combinations as a code bit pair and producing a signal for identifying a fourth coding state, and additional logic means for providing at least nine encoding states for operating in a (4,3) code.

Claim 16

The zero modulation encoder of claim 9 wherein each of said means for providing said signal for identifying the resulting encoding state comrpises, means for providing a three bit signal and said encoder further includes means for storing said code bit pairs from one encoding operation and supplying said code bit pair to said plurality of logic means on a next encoding operation to further identify one of said nine states.