Method of fabricating injection logic integrated circuits using oxide isolation

Claim 1

IN A METHOD FOR FABRICATING A SEMICONDUCTOR INTEGRATED INJECTION LOGIC CELL STRUCTURE HAVING AN INJECTION TRANSISTOR AND A COMPLEMENTARY SWITCHING TRANSISTOR INCLUDING THE STEPS OF FORMING ON A SEMICONDUCTOR BULK PORTION OF A FIRST CONDUCTIVITY TYPE A SEMICONDUCTOR EPITAXIAL LAYER OF THE SAME CONDUCTIVITY TYPE AND HAVING A LOWER CONCENTRATION OF FIRST CONDUCTIVITY TYPE IMPURITIES THAN THE BULK PORTION AND FORMING IN THE SEMICONDUCTOR A LATERAL AND AN INVERTED TRANSISTOR, THE IMPROVEMENT BEING THE STEPS OF FORMING AT LEAST ONE REGION OF OXIDE ISOLATION EXTENDING PARTIALLY THROUGH THE THICKNESS OF THE EPITAXIAL LAYER AND LATERALLY SURROUNDING AND ISOLATING PORTIONS OF THE EPITAXIAL LAYER SO THE EPITAXIAL LAYER IS SUITABLE FOR USE AS AN EMITTER FOR THE SWITCHING TRANSISTOR AND THE PORTION OF THE EPITAXIAL LAYER IN THE REMAINING THICKNESS IS SUITABLE FOR USE LATERAL BASE FOR THE INJECTION TRANSISTOR, INTRODUCING IMPURITIES OF A SECOND CONDUCTIVITY TYPE INTO THE PORTIONS OF THE EPITAXIAL LAYER LATERALLY SURROUNDED BY THE OXIDE ISOLATION REGION TO FORM ONE ZONE SUITABLE FOR USE AS AN EMITTER FOR THE INJECTOR TRANSISTOR AND ANOTHER ZONE SUITABLE FOR USE BOTH AS A COLLECTOR FOR THE INJECTOR TRANSISTOR AND A BASE FOR THE SWITCHING TRANSISTOR, FORMING AN INTERCONNECTION PATTERN COMPRISING REGIONS OF POLYCRYSTALLINE SILICON CONTAINING IMPURTIES OF THE FIRST CONDUCTIVITY TYPE PARTIALLY OVERLAPPING BOTH THE OXIDE ISOLATION REGION AND ONE OF THE ISOLATED PORTION OF THE EPITAXIAL LAYER, AND DIFFUSING IMPURITIES OF THE FIRST CONDUCTIVITY TYPE FROM THE INTERCONNECTION PATTERN INTO THE UNDERLYING SEMICONDUCTIVE MATERIAL TO FORM AT LEAST ONE IMPURTIY POCKET SUITABLE FOR USE AS A COLLECTOR FOR THE SWITCHING TRANSISTOR.