Surface charge storage and transfer devices

Claim 2

IN COMBINATION A SUBSTRATE OF ONE CONDUCTIVITY TYPE SEMICONDUCTOR MATERIAL WITH A SURFACE ADJACENT PORTION INCLUDING A THIN CONTINUOUS CHANNEL REGION OF OPPOSITE CONDUCTIVITY TYPE OF SUBSTANTIALLY UNIFORM DEPTH AND HAVING SUBSTANTIALLY UNIFORM NET DOPANT CONCENTRATION ALONG ITS LENGTH, AN INSULATOR LAYER OVERLYING SAID SURFACE ADJACENT PORTION, A PLURALITY OF CONDUCTOR MEMBERS OVERLYING SAID INSULATOR LAYER AND SAID REGION OF OPPOSITE CONDUCTIVITY TYPE AND SPACED ALONG THE LENGTH OF SAID CHANNEL REGION, BIASING MEANS FOR APPLYING PHASE RELATED VOLTAGES TO SAID CONDUCTOR MEMBER IN RELATION TO SAID SUBSTRATE TO FORM A PLURALITY OF CHARGE STORAGE REGIONS FOR OPPOSITE CONDUCTIVITY CARRIERS IN SAID CHANNEL REGION, MEANS FOR INTRODUCING CHARGE OF OPPOSITE CONDUCTIVITY CARRIERS REPRESENTING A SIGNAL INTO ONE OF SAID CHARGE STORAGE REGIONS, SAID PHASE RELATED VOLTAGES APPLIED TO SAID CONDUCTOR MEMBERS INCREMENTALLY MOVING CHARGE OF OPPOSITE CONDUCTIVITY CARRIERS FROM STORAGE REGION TO STORAGE REGION ALONG SAID CHANNEL, MEANS FOR REMOVING CHARGE OF OPPOSITE CONDUCTIVITY CARRIERS FROM ANOTHER ONE OF SAID STORAGE REGIONS.

Claim 3

The combination of claim 1 in which said spaced conductor members are formed into a first and second group, each conductor member of said second group is spaced between respective adjacently spaced conductor members of said first group, and in which said biasing means includes a first pair of phase related voltages applied to said first group of conductor members to form a plurality of charge storage regions thereunder and also includes a second pair of phase related voltages applied to said second group of conductor members to form a plurality of non-conducting barrier regions thereunder, each pair of adjacent storage regions being separated by a respective barrier region.

Claim 4

The combination of claim 2 including means for rendering adjacent barrier regions alternately conductive whereby electrical charges are transferred along said channel region of opposite conductivity from storage region to storage region.

Claim 5

The combination of claim 1 in which said spaced conductor members are formed into a first, second and third group of conductor members, each third succeeding conductor member included in a respective group, and in which said biasing means includes first, second and third phase related voltages applied to said first, second and third group of conductor members respectively to incrementally move charge along said channel region of opposite conductivity type.

Claim 6

The combination of claim 1 in which said biasing means reversely biases the PN junction between said substrate of one conductivity type and said channel region of opposite conductivity type.

Claim 7

The combination of claim 1 in which said means for introducing charge into said one storage region includes a variable bias means for controlling the potential of a zone of said channel region of opposite conductivity type adjacent said one storage region.

Claim 8

The combination of claim 1 in which said means for removing charge from said one storage region includes bias means for controlling the potential of a zone of said channel region of opposite conductivity type adjacent said other storage region.

Claim 9

The combination of claim 1 in which said spaced conductor members are formed into a first, second, third and fourth group of conductors, each fourth succeeding conductor member included in a respective group, and in which said biasing means includes first, second, third and fourth phase related voltages applied to said first, second, third and fourth group of conductor members respectively to incrementally move charge along said channel region of opposite conductivity type.

Claim 10

In combination, a substrate on one conductivity type semiconductor material with a surface adjacent portion including a continuous channel region of opposite conductivity type, an insulator layer overlying said surface adjacent portion, a plurality of conductor members overlying said insulator layer and said channel region of opposite conductivity type and spaced along the length of said channel region, means for biasing said conductor members in relation to said substrate and in relation to said channel region of opposite conductivity type to form a plurality of charge storage regions for opposite conductivity carriers in said channel region of opposite conductiviTy type, a second region of said one conductivity type lying within said channel region of opposite conductivity type to form a transistor in which said second region is the emitter, said channel region of opposite conductivity type forming a PN junction with said second region is the base and said substrate is the collector, means for applying a voltage in circuit with said second region and said substrate to forwardly bias said second region of one conductivity with respect to said channel region of opposite conductivity type and to reversely bias said channel region of opposite conductivity type with respect to said substrate, means for conducting charge introduced into said one storage region along said channel region of opposite conductivity type into the base of said transistor, means connected in circuit with said second region of one conductivity type and said substrate for sensing the current flow in said transistor in response to the flow of said charge.

Claim 11

In combination, a substrate on one conductivity type semiconductor material with a surface adjacent portion including a continuous channel region of opposite conductivity type, an insulator layer overlying said surface adjacent portion, a plurality of conductor members overlying said insulator layer and said channel region of opposite conductivity type and spaced along the length of said channel region, means for biasing said conductor members in relation to said substrate and in relation to said channel region of opposite conductivity type to form a plurality of charge storage regions for opposite conductivity carriers in said channel region of opposite conductiviTy type, a second region of said one conductivity type lying within said channel region of opposite conductivity type to form a transistor in which said second region is the emitter, said channel region of opposite conductivity type forming a PN junction with said second region is the base and said substrate is the collector, means for applying a voltage in circuit with said second region and said substrate to forwardly bias said second region of one conductivity with respect to said channel region of opposite conductivity type and to reversely bias said channel region of opposite conductivity type with respect to said substrate, means for conducting charge introduced into said one storage region along said channel region of opposite conductivity type into the base of said transistor, means connected in circuit with said second region of one conductivity type and said substrate for sensing the current flow in said transistor in response to the flow of said charge.