US3676715A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor apparatus for image sensing and dynamic storage
Assignee: AT&T Inc
•
Filing: 1970-06-26
•
Granted: 1972-07-11
•
Expires: 1990-06-26
Abstract
Abstract Semiconductor apparatus for use in image sensing and/or dynamic storage applications. The apparatus includes a matrix of basic functional elements, each element including an MIS surface portion and an underlying PN junction. Conduction paths associated with each row and column of the matrix enable interrogation of the basic elements in either word organized or bit organized fashion. In operation, minority carriers are temporarily stored in surface inversion layers associated with each MIS portion after having been photogenerated or electronically injected from the underlying PN junction. Interrogation is accomplished by removing the voltage across an MIS portion to release the stored minority carriers and reversebiasing the underlying junction to collect the released carriers.
Inventors
- 👤 Samuel Brojdo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 13:23
CPC Classifications
H; H10; H10F; H10F39/00; H10F39/10; H10F39/12; H10F39/18; H10B; H10B12/00
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
209 words
Semiconductor apparatus comprising: a semiconductor body having a plurality of elongated, mutually parallel rectifying barriers included therein and spaced within a minority carrier diffusion length of a major surface thereof; an insulating layer overlying and contiguous with the major surface of the body, said layer being relatively thick except for a plurality of localized relatively thin portions which are disposed in rows and columns such that each column overlies a common rectifying barrier; means forming a plurality of row conduction paths disposed over the insulating layer and extending substantially orthogonally with respect to the rectifying barriers, a separate one of the row conduction paths overlying the thin insulating portions of each row; means for applying voltages to the row conduction paths sufficient to induce nonequilibrium depletion regions under the thin insulating portions; means for generating and storing charge carriers in a plurality of the depletion regions; means for reverse-biasing the rectifying barriers; and means for collapsing the depletion regions under individual ones of the row conduction paths while maintaining the depletion regions under the other row conduction paths and for simultaneously maintaining the reverse bias upon the rectifying barriers so that the charge carriers are released by the collapsing depletion regions and are collected by the underlying rectifying barriers.
Claim 2
Dependent Claim
209 words
Semiconductor apparatus comprising: a semiconductor body having a plurality of elongated, mutually parallel rectifying barriers included therein and spaced within a minority carrier diffusion length of a major surface thereof; an insulating layer overlying and contiguous with the major surface of the body, said layer being relatively thick except for a plurality of localized relatively thin portions which are disposed in rows and columns such that each column overlies a common rectifying barrier; means forming a plurality of row conduction paths disposed over the insulating layer and extending substantially orthogonally with respect to the rectifying barriers, a separate one of the row conduction paths overlying the thin insulating portions of each row; means for applying voltages to the row conduction paths sufficient to induce nonequilibrium depletion regions under the thin insulating portions; means for generating and storing charge carriers in a plurality of the depletion regions; means for reverse-biasing the rectifying barriers; and means for collapsing the depletion regions under individual ones of the row conduction paths while maintaining the depletion regions under the other row conduction paths and for simultaneously maintaining the reverse bias upon the rectifying barriers so that the charge carriers are released by the collapsing depletion regions and are collected by the underlying rectifying barriers.
Claim 3
Dependent Claim
13 words
Apparatus as recited in claim 1 wherein the rectifying barriers are PN junctions.
Claim 4
Dependent Claim
219 words
Semiconductor apparatus comprising a semiconductor wafer including: a semiconductive bulk portion of a first type semiconductivity; a plurality of elongated substantially parallel zones, each of substantially greater length than width and each of a second type semiconductivity disposed in the bulk portion and forming a corresponding plurality of PN junctions therewith; a layer of the first type semiconductivity disposed over and contiguous with the bulk portion such that the surface of the layer is a surface of the wafer and such that the thickness of the layer is less than a diffusion length for minority carriers in the layer; means including said layer of first conductivity type forming a plurality of Metal-Insulator-Semiconductor devices disposed in rows and columns over the elongated zones such that the layer provides a common semiconductive portion for each of the Metal-Insulator-Semiconductor devices, each column of devices being disposed over a common one of the zones; a plurality of means forming row conduction paths substantially orthogonally to the elongated zones, each of which paths provides a common electrical contact to the metal portion of each Metal-Insulator-Semiconductor deviCe in a given row; a plurality of low resistance electrical contacts, separate ones providing low resistance contact to separate ones of the elongated zones; and a separate electrical contact to the semiconductive portion of the first type semiconductivity.
Claim 5
Dependent Claim
219 words
Semiconductor apparatus comprising a semiconductor wafer including: a semiconductive bulk portion of a first type semiconductivity; a plurality of elongated substantially parallel zones, each of substantially greater length than width and each of a second type semiconductivity disposed in the bulk portion and forming a corresponding plurality of PN junctions therewith; a layer of the first type semiconductivity disposed over and contiguous with the bulk portion such that the surface of the layer is a surface of the wafer and such that the thickness of the layer is less than a diffusion length for minority carriers in the layer; means including said layer of first conductivity type forming a plurality of Metal-Insulator-Semiconductor devices disposed in rows and columns over the elongated zones such that the layer provides a common semiconductive portion for each of the Metal-Insulator-Semiconductor devices, each column of devices being disposed over a common one of the zones; a plurality of means forming row conduction paths substantially orthogonally to the elongated zones, each of which paths provides a common electrical contact to the metal portion of each Metal-Insulator-Semiconductor deviCe in a given row; a plurality of low resistance electrical contacts, separate ones providing low resistance contact to separate ones of the elongated zones; and a separate electrical contact to the semiconductive portion of the first type semiconductivity.
Claim 6
Dependent Claim
86 words
Apparatus as recited in claim 3 wherein the plurality of Metal-Insulator-Semiconductor devices includes: an insulating layer overlying and contiguous with the surface of the wafer, said insulating layer including relatively thick portions and a plurality of relatively thin portions, each thin portion providing the insulating portion of one of the Metal-Insulator-Semiconductor devices; and a plurality of spaced localized metallic regions, each overlying and being contiguous with a separate one of the thin insulating portions and each providing the metallic portion of one of the Metal-Insulator-Semiconductor devices.
Claim 7
Dependent Claim
32 words
Apparatus as recited in claim 4 wherein each of the plurality of conduction paths is at least semitransparent and each of the plurality of spaced localized metallic regions is at least semitransparent.
Claim 8
Dependent Claim
30 words
Apparatus as recited in claim 3 wherein the semiconductive portion of the Metal-Insulator-Semiconductor portion is electrically and physically common with the semiconductive material comprising one side of the PN junctions.
Claim 9
Dependent Claim
32 words
Apparatus as recited in claim 3 wherein the semiconductive portion of the Metal-Insulator-Semiconductor portion comprises a semiconductive layer, which layer also constitutes the semiconductive material comprising one side of the PN junctions.
Claim 10
Dependent Claim
21 words
Apparatus as recited in claim 7 wherein the layer is at least as thick as an absorption length for visible light.
Claim 11
Dependent Claim
18 words
Apparatus as recited in claim 8 wherein the layer is of thickness between about 1 and 25 microns.
Claim 12
Dependent Claim
213 words
Apparatus as recited in claim 3 further comprising: means for applying a first voltage between the zones and the semiconductive material of the first type conductivity sufficient to reverse bias the PN junctions; means for applying a second voltage to a plurality of the row conduction paths sufficient to form depletion regions completely through the layer under each of the Metal-Insulator-Semiconductor structures connected to said plurality of row conduction paths, such that a ''''write 0'''' operation is accomplished; means for applying a third voltage to one of the row conduction paths and for removing the first applied voltage from at least one of the PN junctions, the third voltage being of greater magnitude than the second voltage and being sufficiently large to indirectly forward bias that portion of said at least one PN junction underlying said one row conduction path sufficiently that minority carriers are injected by said portion of said at least one PN junction across the layer and are accumulated at the semiconductor-insulator interface opposite said portion of the PN junction; and means for removing said third voltage and for reapplying said second voltage to said one row conduction path and for reapplying said first voltage to said at least one PN junction, such that a ''''write 1'''' operation is accomplished.
Claim 13
Independent Claim
305 words
A method of operating in the Base Depletion Mode apparatus of the type including a semiconductor body having a plurality of elongated, mutually parallel rectifying barriers, included therein and spaced within a minority carrier diffusion length of a major surface thereof; an insulating layer overlying and contiguous with the major surface of the body, said layer being relatively thick except for a plurality of localized, relatively thin portions disposed in rows and columns such that each column overlies a common rectifying barrier; a plurality of means forming row conduction paths disposed over the insulating layer and extending substantially orthogonally with respect to the rectifying barriers such that a separate one of the row conduction paths overliEs the thin insulating portions of each row; the method comprising the steps of: applying a first voltage of polarity and magnitude sufficient to reverse bias a plurality of the rectifying barriers; applying a second voltage to a plurality of the row conduction paths sufficient to form nonequilibrium depletion regions extending from the surface to the rectifying barrier thereunder, such that a ''''write 0'''' operation is accomplished; applying a third voltage to one of said plurality of row conduction paths and removing the first applied voltage from at least one of the rectifying barriers, the third voltage being of greater magnitude than the second voltage and being sufficiently large to indirectly forward bias that portion of said at least one rectifying barrier underlying said row conduction path such that minority carriers are injected by said portion of said at least one rectifying barrier through said nonequilibrium depletion region and are accumulated at the semiconductor-insulator interface; and removing said third voltage; reapplying said second voltage to said one row conduction path; and reapplying said first voltage to said at least one rectifying barrier, such that a ''''write 1'''' operation is accomplished.
Claim 14
Independent Claim
305 words
A method of operating in the Base Depletion Mode apparatus of the type including a semiconductor body having a plurality of elongated, mutually parallel rectifying barriers, included therein and spaced within a minority carrier diffusion length of a major surface thereof; an insulating layer overlying and contiguous with the major surface of the body, said layer being relatively thick except for a plurality of localized, relatively thin portions disposed in rows and columns such that each column overlies a common rectifying barrier; a plurality of means forming row conduction paths disposed over the insulating layer and extending substantially orthogonally with respect to the rectifying barriers such that a separate one of the row conduction paths overliEs the thin insulating portions of each row; the method comprising the steps of: applying a first voltage of polarity and magnitude sufficient to reverse bias a plurality of the rectifying barriers; applying a second voltage to a plurality of the row conduction paths sufficient to form nonequilibrium depletion regions extending from the surface to the rectifying barrier thereunder, such that a ''''write 0'''' operation is accomplished; applying a third voltage to one of said plurality of row conduction paths and removing the first applied voltage from at least one of the rectifying barriers, the third voltage being of greater magnitude than the second voltage and being sufficiently large to indirectly forward bias that portion of said at least one rectifying barrier underlying said row conduction path such that minority carriers are injected by said portion of said at least one rectifying barrier through said nonequilibrium depletion region and are accumulated at the semiconductor-insulator interface; and removing said third voltage; reapplying said second voltage to said one row conduction path; and reapplying said first voltage to said at least one rectifying barrier, such that a ''''write 1'''' operation is accomplished.
Claim 15
Dependent Claim
80 words
A method as recited in claim 11 further comprising the steps of: removing said second voltage from one of said row conduction paths while maintaining said first voltage across said plurality of rectifying barriers so that minority carriers accumulated in the depletion regions under said one row conduction path are released from the semiconductor-insulator interface and are collected by said rectifying barriers; and detecting the carriers collected by each of said rectifying barriers, such that a word-organized read-out is accomplished.
Claim 16
Independent Claim
275 words
A method of operating as an image sensor apparatus of the type including a semiconductor body having a plurality of elongated, mutually parallel rectifying barriers included therein and spaced within a minority carrier diffusion length of a major surface thereof; an insulating layer overlying and contiguous with the major surface of the body, said layer being relatively thick except for a plurality of localized, relatively thin portions disposed in rows and columns such that each column overlies a common rectifying barrier; means forming a plurality of row conduction paths disposed over the insulating layer and extending substantially orthogonally with respect to the rectifying barriers such that a separate one of the row conduction paths overlies the thin insulating portions of each row; the method comprising the steps of: applying a first voltage of polarity and magnitude sufficient to reverse bias a plurality of the rectifying barriers; applying a second voltage to a plurality of row conduction paths sufficient to form nonequilibrium depletion regions thereunder adjacent the surface of the semiconductor body and extending less than the distance to the rectifying barriers thereunder; exposing the apparatus to radiant energy of wavelength and intensity sufficient to generate hole-electron pairs in and near said depletion regions; removing the second voltage from one of said row conduction paths while maintaining the reverse bias on said plurality of rectifying barriers in a manner sufficient that photogenerated minority carriers are released from the semiconductor-insulator surface under said one row of conduction path and so that said released minority carriers are collected by the underlying rectifying barriers; and detecting separately the minority carriers collected by at least one of the rectifying barriers.
Claim 17
Independent Claim
275 words
A method of operating as an image sensor apparatus of the type including a semiconductor body having a plurality of elongated, mutually parallel rectifying barriers included therein and spaced within a minority carrier diffusion length of a major surface thereof; an insulating layer overlying and contiguous with the major surface of the body, said layer being relatively thick except for a plurality of localized, relatively thin portions disposed in rows and columns such that each column overlies a common rectifying barrier; means forming a plurality of row conduction paths disposed over the insulating layer and extending substantially orthogonally with respect to the rectifying barriers such that a separate one of the row conduction paths overlies the thin insulating portions of each row; the method comprising the steps of: applying a first voltage of polarity and magnitude sufficient to reverse bias a plurality of the rectifying barriers; applying a second voltage to a plurality of row conduction paths sufficient to form nonequilibrium depletion regions thereunder adjacent the surface of the semiconductor body and extending less than the distance to the rectifying barriers thereunder; exposing the apparatus to radiant energy of wavelength and intensity sufficient to generate hole-electron pairs in and near said depletion regions; removing the second voltage from one of said row conduction paths while maintaining the reverse bias on said plurality of rectifying barriers in a manner sufficient that photogenerated minority carriers are released from the semiconductor-insulator surface under said one row of conduction path and so that said released minority carriers are collected by the underlying rectifying barriers; and detecting separately the minority carriers collected by at least one of the rectifying barriers.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-07-11 | 1976-01-10 | 1976-07-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-07-11 | 1980-01-10 | 1980-07-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-07-11 | 1984-01-10 | 1984-07-11 | $7700.00 | Window Closed / Lapsed |