US3900833A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Data communication system
Assignee: Singer Co
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Filing: 1974-03-18
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Granted: 1975-08-19
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Expires: 1994-03-18
Abstract
Abstract A digital data communication system is provided which includes a subsystem having a multiplicity of encoder/decoder interface modules which may be cross-connected to permit redundant interconnection of portions of the modules to allow two or more such portions to be paralleled to constitute a high reliability system. The individual modules, in accordance with the invention, are constructed to be micro programmable by means of a read-only memory which enables received control words to be divided into their individual sections, or fields, and which permits the individual fields to be separately steered into designated logical elements connected in parallel between a common receive bus and a common transmit bus. The system is capable of processing a wide variety of word formats, and any designated word sections, regardless of bit lengths, within the capabilities of the individual logic elements.
Inventors
- 👤 R Timothy Rogers
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 15:13
CPC Classifications
H; H04; H04B; H04B1/00; H04B1/74; G; G06; G06F; G06F13/00; G06F13/38; G06F13/382; G06F13/385
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
99 words
In a digital data transmission system, an interface module for coupling a subsystem, or the like, to a common communication link and which includes: a receiving section having a decoder for accepting and detecting multi-section control words and data words; a common bus connected to said decoder in said receiving section for receiving detected control words and data words from the decoder; a plurality of logic elements having inputs parallel coupled to said common bus; and logic circuitry connected to said logic elements for steering the individual sections of the control word into different ones of said logic elements.
Claim 2
Dependent Claim
99 words
In a digital data transmission system, an interface module for coupling a subsystem, or the like, to a common communication link and which includes: a receiving section having a decoder for accepting and detecting multi-section control words and data words; a common bus connected to said decoder in said receiving section for receiving detected control words and data words from the decoder; a plurality of logic elements having inputs parallel coupled to said common bus; and logic circuitry connected to said logic elements for steering the individual sections of the control word into different ones of said logic elements.
Claim 3
Dependent Claim
30 words
The combination defined in claim 1, and which includes register means coupled to said common bus, and in which said logic circuitry steers received data words into said register means.
Claim 4
Dependent Claim
57 words
The cOmbination defined in claim 1, and which includes read-only memory means included in said logic circuitry to program said logic circuitry to any particular format of the received control words and to permit the individual sections of the received control words to be steered by said logic circuitry into predetermined different ones of said logic elements.
Claim 5
Dependent Claim
68 words
The combination defined in claim 2, and which includes read-only memory means to program said logic circuitry to any particular format of the received control words and data words, and to permit the individual sections of the received control words to be steered by said logic circuitry into predetermined different ones of said logic elements and to permit said data words to be steered into said register means.
Claim 6
Dependent Claim
71 words
The combination defined in claim 1, and which includes a transmitting section having an encoder; a second common bus connected to the encoder in said transmitting section and to which the outputs of said logic elements are parallel coupled; and in which said logic circuitry is controllable to select signals from different ones of said logic elements in a controllable sequence for application to said encoder by said second common bus.
Claim 7
Dependent Claim
43 words
The combination defined in claim 5, and which includes read-only memory means included in said logic circuitry to program said logic circuitry to any particular format of the sequence in which signals from said logic elements are to be supplied to said encoder.
Claim 8
Dependent Claim
56 words
The combination defined in claim 6, in which said read-only memory means also serves to program said logic circuitry to any particular format of the received control words and data words, and to divide the received control words into individual sections to be steered by said logic circuitry into predetermined different ones of said logic elements.
Claim 9
Dependent Claim
83 words
The combination defined in claim 7, and which includes register means having its input connected to the first-named common bus and its output connected to the second common bus, and in which said read-only memory means programs the logic circuitry to steer received data words into said register means during a receive mode of the module, and to steer data words out of said register means to the second common bus for application to said decoder during a transmit mode of the module.
Claim 10
Dependent Claim
45 words
The combination defined in claim 8, in which said logic elements include a mode block, and in which the received control words include a mode-designating section to be steered by said logic circuitry into said mode block to determine the transmit/receive mode of the module.
Claim 11
Dependent Claim
54 words
The combination defined in claim 5, and which includes a plurality of like modules each connected to a different data link; and crossover circuitry to permit the encoder and decoder and associated logic elements of each of said modules to be redundantly interconnected to allow for said modules to be paralleled for high reliability.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-08-18 | 1979-02-17 | 1979-08-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-08-18 | 1983-02-17 | 1983-08-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-08-18 | 1987-02-17 | 1987-08-19 | $7700.00 | Window Closed / Lapsed |