US3731275A
Expired / Lapsed
US
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Digital switching network
Assignee: Telent Technologies Services Ltd
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Filing: 1971-09-03
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Granted: 1973-05-01
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Expires: 1991-09-03
Abstract
Abstract A solid state semiconductor matrix switch for transmitting digital data from a set of input-output leads to any one of a number of output-input leads includes circuitry for marking and selecting cross point circuits through the network of the switch. In addition, circuitry for holding selected crosspoints after mark signals have been removed is employed. Typically, the switch includes an 8 X 8 matrix array of cross point circuits which are capable of providing eight individual paths through the matrix, no two operated crosspoints being located in any vertical or horizontal matrix strip. In addition, a circuit for checking the vertical matrix strips to determine which of the crosspoint circuits are completed is included. Also, an error checking system is employed to determine if more than a single crosspoint circuit in any one of the vertical matrix strips is operates.
Inventors
- 👤 P Lenk
- 👤 W Dunn
- 👤 R Mina
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 04:37
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17748; H03K19/17764; G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/085; H03K19/17736
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
115 words
A digital switching network comprising: a plurality of crosspoint circuits arranged in a matrix array forming horizontal and vertical strips respectively, and having two pairs of input and output connections for receiving and sending digital data signals through each of the respective inputs and outputs ; means , connected to said crosspoint circuits of said matrix array, for marking and seizing the crosspoint circuits within said matrix array, through which a digital data path is to be provided; and means, connected to said matrix array, for detecting the number of operated crosspoint circuits within individual strips and for providing an error signal indicating the operation of other than a single crosspoint circuit within one strip.
Claim 2
Dependent Claim
115 words
A digital switching network comprising: a plurality of crosspoint circuits arranged in a matrix array forming horizontal and vertical strips respectively, and having two pairs of input and output connections for receiving and sending digital data signals through each of the respective inputs and outputs ; means , connected to said crosspoint circuits of said matrix array, for marking and seizing the crosspoint circuits within said matrix array, through which a digital data path is to be provided; and means, connected to said matrix array, for detecting the number of operated crosspoint circuits within individual strips and for providing an error signal indicating the operation of other than a single crosspoint circuit within one strip.
Claim 3
Dependent Claim
62 words
A digital switching network according to claim 1, wherein said error signal providing means comprises means , connected to each crosspoint circuit, for preventing said error signal from being provided in response to multiple crosspoint circuits in said matrix array being operated, as long as each respective horizontal and vertical strip of crosspoint circuits has only a single croSspoint circuit therein operated.
Claim 4
Dependent Claim
67 words
A digital switching network according to claim 1, wherein each crosspoint within said matrix array further includes terminal connections for marking and seizing paths therefor and wherein each network further includes binary reduction circuitry connected to the respective mark terminals of each crosspoint circuit within said array so as to substantially reduce the number of external terminals required for energizing any selected crosspoint circuit within said array.
Claim 5
Dependent Claim
83 words
A digital switching network according to claim 3, wherein each crosspoint circuit comprises matrix gating circuitry having a first gating circuit to one input of which a crosspoint circuit holding signal is applied through said seizing means for seizing said crosspoint circuit, and a second gating circuit, the output of which is coupled to an input of said first gating circuit, having its inputs connected to said marking means for marking a selected crosspoint circuit through which data signals are to be transmitted.
Claim 6
Dependent Claim
63 words
A digital switching network according to claim 4, wherein each crosspoint circuit further includes a pair of transmission gate circuits, responsive to the output of said second gating circuit, for coupling data signals, applied to the data lines associated with said crosspoint circuits , through said crosspoint circuits , whereby a marked and seized crosspoint circuit may send and receive data signals therethrough.
Claim 7
Dependent Claim
62 words
A digital switching network according to claim 5, wherein each crosspoint circuit further includes a third gating circuit responsive to the outputs of said first and second gating circuits for disabling said pair of transmission gate circuits upon the release of said first and second gating circuits, in response to the absence of crosspoint circuit holding and marking signals applied respectively thereto.
Claim 8
Dependent Claim
65 words
A digital switching network according to claim 6, wherein each row of crosspoint circuits within said matrix array further includes a fourth gating circuit connected to the output of each first gating circuit connected to the output of each first gating circuit within the respective crosspoint circuits of said row for providing an output holding signal, whenever any crosspoint circuit within said row is seized.
Claim 9
Dependent Claim
68 words
A digital switch network according to claim 6, wherein each row of crosspoint circuits within said matrix array further includes a fifth gating circuit connected to the outputs of each said third gating circuit within said row for providing a crosspoint circuit enabled signal to said error detecting means in response to a crosspoint circuit marking signal applied to any of said third gating circuits within said row.
Claim 10
Dependent Claim
50 words
A digital switching network according to claim 8, wherein said error detecting means includes a first plurality of logic gates responsive to the outputs of each of said fifth gating circuits for providing a first error signal in response to the energization of more than a single fifth gating circuit.
Claim 11
Dependent Claim
48 words
A digital switching network according to claim 9, wherein said error detecting means further includes a sixth gating circuit responsive to the outputs of each of said fifth gating circuits for providing a second error signal in response to the energization of none of said fifth gating circuits.
Claim 12
Dependent Claim
52 words
A digital switching network according to claim 10, wherein said error detecting circuit further includes a seventh gating circuit responsive to the outputs of said first plurality of logic gates and said sixth gating circuit for generating a fault indication signal in response to either of said first or second error signals.
Claim 13
Dependent Claim
42 words
A digital switching network according to claim 9, wherein said error detecting means further includes a second plurality of logic gates responsive to the outputs of each of said fifth gating circuits for providing fault location signals representing improperly energized crosspoint circuits.
Claim 14
Dependent Claim
44 words
A digital switching network according to claim 11, further including fault cheCking and mark enabling gate circuits connected to said binary reduction circuitry and said seventh gating circuit for enabling the application of mark signals to said crosspoint circuits and said fault indication signal.
Claim 15
Dependent Claim
89 words
In a digital switching network having a plurality of crosspoint circuits arranged in a matrix array, forming horizontal and vertical matrix strips respectively, input and output connections applied thereto for receiving and sending digital data signals therethrough and means for operating at least one of said crosspoint circuits in said matrix, through which a digital data path is to be provided, an error checking arrangement comprising means, responsive to the operation of each of said crosspoint circuits, for determining whether only one crosspoint circuit per matrix strip is operating.
Claim 16
Dependent Claim
89 words
In a digital switching network having a plurality of crosspoint circuits arranged in a matrix array, forming horizontal and vertical matrix strips respectively, input and output connections applied thereto for receiving and sending digital data signals therethrough and means for operating at least one of said crosspoint circuits in said matrix, through which a digital data path is to be provided, an error checking arrangement comprising means, responsive to the operation of each of said crosspoint circuits, for determining whether only one crosspoint circuit per matrix strip is operating.
Claim 17
Dependent Claim
39 words
An error checking arrangement according to claim 14, comprising means, responsive to the operation of a crosspoint circuit within a matrix strip, for identifying the location of the matrix strip orthogonal thereto in which said crosspoint circuit is located.
Claim 18
Dependent Claim
29 words
An error checking arrangement according to claim 14, wherein each crosspoint circuit within said matrix array includes terminal connections for marking, seizing and data sending and receiving paths therethrough.
Claim 19
Dependent Claim
83 words
An error checking arrangement according to claim 14, wherein each crosspoint circuit comprises matrix gating circuitry having a first gating circuit to one input of which a crosspoint circuit holding signal is applied through said seizing means for seizing said crosspoint circuit, and a second gating circuit, the output of which is coupled to an input of said first gating circuit, having its inputs connected to said marking means for marking a selected crosspoint circuit through which data signals are to be transmitted.
Claim 20
Dependent Claim
59 words
An error checking arrangement according to claim 17, wherein each crosspoint further includes a pair of transmission gate circuits responsive to the output of said second gating circuit, for coupling data signals applied to the data lines associated with said crosspoints , through said crosspoint circuits, whereby seized and marked crosspoint circuit may send and receive data signals therethrough.
Claim 21
Dependent Claim
62 words
An error checking arrangement according to claim 18, wherein each crosspoint circuit further includes a third gating circuit responsive to the outputs of said first and second gating circuits for disabling said pair of transmission gate circuits upon the release of said first and second gating circuits, in response to the absence of crosspoint circuit holding and marking signals applied respectively thereto.
Claim 22
Dependent Claim
56 words
An error checking arrangement according to claim 19, wherein each row of crosspoint circuits within said matrix array further includes a fourth gating circuit connected to the output of each first gating circuit within the respective crosspoint circuit of said row for providing an output holding signal, whenever any crosspoint circuit within said row is seized.
Claim 23
Dependent Claim
69 words
An error checking arrangement according to claim 20, wherein each row of crosspoint circuits within said matrix array further includes a fifth gating circuit connected to the outputs of each of said third gating circuit within said row for providing a crosspoint circuit enabled signal to said error detecting means in response to a crosspoint circuit marking signal applied to any of said third gating circuits within said row.
Claim 24
Dependent Claim
49 words
In a digital switching network according to claim 14, wherein said error detecting arrangement includes a first plurality of logic gates responsive to the outputs of each crosspoint for generating a first error signal in response to the energization of more than a single crosspoint circuit within any strip.
Claim 25
Dependent Claim
45 words
In a digital switching network according to claim 14, wherein said error detecting arrangement further includes a logic circuit responsive to the outputs of each of said crosspoint circuits for generating an error signal in response to the energizatIon of none of said crosspoint circuits.
Claim 26
Dependent Claim
46 words
In a digital switching network according to claim 22, wherein said error detecting arrangement further includes a logic circuit responsive to the outputs of each of said crosspoint circuits for generating a second error signal in response to the energization of none of said crosspoint circuits.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-04-30 | 1976-10-30 | 1977-05-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-04-30 | 1980-10-30 | 1981-05-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-04-30 | 1984-10-30 | 1985-05-01 | $7700.00 | Window Closed / Lapsed |