Time division switching system

Claim 2

A time division switching system wherein m time slots occur in repetitive frames, each time slot being divided into a plurality of bit intervals and each bit interval being subdivided into n positions comprising a first group of k time division paths, a second group of l time division paths, k < or = l, crosspoint means interconnecting each time division path of the first group with the time division paths of the second group, and control means for selectively enabling said crosspoint means to transfer information bits from the time division paths of said first group to the time division paths of the second group in each position, said control means comprising a control memory for each path of the group having k paths for storing control codes to selectively enable the crosspoint means associated with said control memory, said control memory being adapted to store m control codes, each code having n log2l bits. A a time division switching system wherein m time slots occur in repetitive frames, such time slot being divided into a plurality of bit intervals and each bit interval being divided into n positions according to claim 3 wherein said crosspoint means comprises a plurality of crosspoints, each crosspoint comprising a crosspoint gate connected from one first group time division path to one second group time division path and a register for controlling said gate in each position, and means connected between said crosspoint memory and said crosspoint register for applying control signals corresponding to said control codes to said register.

Claim 3

A time division switching system wherein m time slots occur in repetitive frames, each time slot being divided into a plurality of bit intervals and each bit interval being divided into n positions according to claim 4 wherein said register comprises a recirculating register of n stages each stage being operative to store a bit to control said crosspoint gate in one of said n positions for each time slot, and means for applying the output of said recirculating register to said crosspoint gate in repetitive sequences of n bits during each time slot.

Claim 4

A time division switching system wherein m time slots occur in repetitive frames, each time slot being divided into a plurality of bit intervals and each bit interval being divided into n positions, a first group of k input time division paths, a second group of l intermediate time division paths, a third group of k output time division paths, k < or = la first crosspoint gating network connected between said first and second group for selectively transferring information bits from the time division paths of said first group to the time division paths of said second group in each position, a second crosspoint gating network connected between said second group and said third group for selectively transferring information bits from the time division paths of said second group to the time division paths of said third group in each position, a plurality of control circuits each associated with one path of said first group and a corresponding path of said third group for selectively enabling one of the crosspoint gates connecting said one path of the first group to l paths of said second group and for selectively enabling one of the crosspoint gates connecting said corresponding path of the third group to l paths of said second group in each position, each control circuit comprising a crosspoint gate memory for storing codes to determine the enabling of tHe crosspoint gates connected to said one path and to said corresponding path.

Claim 5

A time division switching system wherein m time slots occur in repetitive frames, each time slot being divided into a plurality of bit intervals and each bit interval being divided into n positions according to claim 6 wherein each crosspoint gate memory includes m codes, each code having n log2l bits, means for reading out said codes sequentially from said memory, one code being read out at the beginning of each time slot, and means responsive to the code readout from said crosspoint memory at the beginning of a time slot for selectively controlling the enabling of each crosspoint gate associated with said one path and each crosspoint gate associated with the corresponding path during said time slot.

Claim 6

A time division switching system wherein m time slots occur in repetitive frames, each time slot being divided into a plurality of bit intervals, and each bit interval being divided into n positions according to claim 7 wherein said selectively controlling means further comprises one crosspoint register connected between a crosspoint gate memory and each crosspoint gate of said first crosspoint gating means for controlling the operation of said crosspoint gate, another crosspoint register being connected between said one crosspoint register and the crosspoint gate associated with the corresponding path for controlling the operation of said crosspoint gate associated with the corresponding path.

Claim 7

A time division switching system wherein m time slots occur in repetitive frames, each time slot being divided into a plurality of bit intervals and each bit interval being divided into n positions according to claim 8 wherein each crosspoint register comprises a recirculating register of n stages for sequentially applying control information to the connected crosspoint gate in each bit interval during a time slot.

Claim 8

A time division switching system wherein m time slots occur in repetitive frames, each time slot being divided into a plurality of bit intervals and each bit interval being divided into n positions according to claim 7 wherein each time division path comprises means for transposing n positions of one bit interval into an arbitrarily designated sequence of n positions in the next succeeding bit interval.

Claim 9

A time division switching system wherein m time slots occur in repetitive frames, each time slot being divided into a plurality of bit intervals and each bit interval being divided into n positions according to claim 10 wherein the transposing means of one input time division path is paired with the transposing means of one output time division path, and further comprising control means connected to each of said paired transposing means, said control means comprising a memory for storing transposition control codes to control the operation of both said input time division path transposing means and said output time division transposing means in each bit interval, and means connected between said control memory and each of the connected transposing means for applying control signals corresponding to said control code in each bit interval to each of said connected transposing means.

Claim 10

A time division switching system wherein m time slots occur in repetitive frames, each time slot being divided into a plurality of bit intervals and each bit interval being divided into n positions, a first group of j input time division paths, a second group of k intermediate time division paths, a third group of j output time division paths, j < or = k, a first crosspoint gating network connected between said first and second groups for selectively transferring information bits from the time division paths of said first group to the time division paths of said second group in each position, a second crosspoint gate network connected between said second group And said third group for selectively transferring information bits from the time division paths of said second group to the time division paths of said third group in each position, a first plurality of control circuits, each associated with one path of said first group for selectively enabling the crosspoint gates connecting said one path of the first group to k paths of the second group, a second plurality of control circuits each associated with one path of said third group for selectively enabling one of the crosspoint gates connecting one path of the third group to k paths of the second group in each position, each control circuit comprising a crosspoint gate memory for storing codes to determine the enabling of the crosspoint gates connected to the path associated with the crosspoint gate memory, each crosspoint gate memory including means for storing m codes, each code having n log2k bits.

Claim 11

A time division switching system comprising first and second groups of time division paths, each path being adapted to transmit interleaved PCM codes in repetitive frames of m time slots, each time slot being divided into a plurality of bit intervals and each bit interval being divided into n channels whereby n PCM codes are transmitted in each time slot, a crosspoint gate network connected between said first group and said second group for selectively transferring PCM code bits from the time division paths of said first group to the time division paths of said second group in each channel, and control means for selectively enabling said crosspoint means in each channel, said control means comprising a control memory for each path of the group having the lesser number of paths, said control memory comprising means for storing m control codes, each code determining the selective enabling of the crosspoints of said control memory path for one of said m time slots, each code having n log2l bits where l is the number of paths in the group having the greater number of paths.