Patent US3898482A successfully refreshed from Google Patents.
US3898482A
Expired / Lapsed
US
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Noise suppression circuit
Assignee: Fairchild Semiconductor Corp
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Filing: 1974-03-29
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Granted: 1975-08-05
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Expires: 1994-03-29
Abstract
Abstract An improved noise suppression circuit which includes a first transistor having a collector, an emitter coupled to the input of the circuit, and a base coupled to an output of the circuit through an impedance means. The circuit includes a second transistor having a base coupled to the collector of the first transistor, a collector coupled to a reference potential, and an emitter integral with the impedance means. The circuit of the present invention can be constructed to suppress positive-going noise pulses, negative-going noise pulses, or one of each can be cascaded to suppress both positive and negative-going noise pulses.
Inventors
- 👤 Jr James G Holt
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 11:33
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/60; H10D84/67; H10D84/673; H10D84/611; H10D84/613
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
173 words
A noise suppression circuit comprising in combination: a. an input means and an output means; b. a first transistor having a collector, an emitter coupled to said input means, and a base coupled to a first impedance means; c. a second transistor having a base coupled to said collector of said first transistor, a collector coupled to a first reference potential, and an emitter integral with said first impedance means; d. a third transistor having an emitter coupled to said first impedance means, a collector, and a base coupled to a second impedance means; e. a fourth transistor having an emitter coupled to said second impedance means, and said output means, a base coupled to the collector of said third transistor, and a collector coupled to a second reference potential; and f. a switching means coupled between said output means and said base of said second transistor, and such that said second transistor is enabled for a first state of said output means and disabled for a second state of said output means.
Claim 2
Dependent Claim
173 words
A noise suppression circuit comprising in combination: a. an input means and an output means; b. a first transistor having a collector, an emitter coupled to said input means, and a base coupled to a first impedance means; c. a second transistor having a base coupled to said collector of said first transistor, a collector coupled to a first reference potential, and an emitter integral with said first impedance means; d. a third transistor having an emitter coupled to said first impedance means, a collector, and a base coupled to a second impedance means; e. a fourth transistor having an emitter coupled to said second impedance means, and said output means, a base coupled to the collector of said third transistor, and a collector coupled to a second reference potential; and f. a switching means coupled between said output means and said base of said second transistor, and such that said second transistor is enabled for a first state of said output means and disabled for a second state of said output means.
Claim 3
Dependent Claim
25 words
A circuit as defined in claim 1 further including a first charge storage means coupled between said base and said collector of said second transistor.
Claim 4
Dependent Claim
25 words
A circuit as defined in claim 1 further including a second charge storage means coupled between said base and said collector of said fourth transistor.
Claim 5
Dependent Claim
27 words
A circuit as defined in claim 1 wherein said first and said fourth transistors are NPN transistors, and said second and said third transistors are PNP transistors.
Claim 6
Dependent Claim
23 words
A circuit as defined in claim 4 wherein said first reference potential is ground and said second reference potential is a positive voltage.
Claim 7
Dependent Claim
15 words
A circuit as defined in claim 1 wherein said second impedance means is a diode.
Claim 8
Dependent Claim
41 words
A circuit as defined in claim 1 wherein said switching means is a transistor having a base said coupled to said output means, a collector coupled to said base of said second transistor, and an emitter coupled to a positive voltage.
Claim 9
Dependent Claim
116 words
Semiconductor structure comprising: a. a substrate of semiconductor material of a first conductivity type; b. a layer of monocrystalline semiconductor material of a second conductivity type formed on said substrate; c. a first region of said first conductivity type formed in said layer of semiconductor material adjacent the top surface of said layer; d. a second region of said second conductivity type formed in said first region; e. an input lead coupled to said second region; f. an output lead means coupled to said first region, whereby said first region comprises the base region of a first transistor, The emitter region of a second transistor, and a resistor between said input lead and said output lead.
Claim 10
Dependent Claim
116 words
Semiconductor structure comprising: a. a substrate of semiconductor material of a first conductivity type; b. a layer of monocrystalline semiconductor material of a second conductivity type formed on said substrate; c. a first region of said first conductivity type formed in said layer of semiconductor material adjacent the top surface of said layer; d. a second region of said second conductivity type formed in said first region; e. an input lead coupled to said second region; f. an output lead means coupled to said first region, whereby said first region comprises the base region of a first transistor, The emitter region of a second transistor, and a resistor between said input lead and said output lead.
Claim 11
Dependent Claim
22 words
Structure as defined in claim 8 wherein said first conductivity type is P conductivity and second conductivity type is N type conductivity.
Claim 12
Dependent Claim
12 words
Structure as defined in claim 8 wherein said semiconductor material is silicon.
Claim 13
Dependent Claim
93 words
A noise suppression circuit comprising in combination: a. an input and an output means; b. an NPN transistor having a collector region, an emitter region coupled to said input means, and a base region coupled to said output means through an impedance means; c. a PNP transistor having a base region coupled to the collector region of said NPN transistor, a collector region coupled to ground potential, and an emitter region integral with said impedance means; and, d. a charge storage means coupled between the base and collector regions of said PNP transistor.
Claim 14
Dependent Claim
93 words
A noise suppression circuit comprising in combination: a. an input and an output means; b. an NPN transistor having a collector region, an emitter region coupled to said input means, and a base region coupled to said output means through an impedance means; c. a PNP transistor having a base region coupled to the collector region of said NPN transistor, a collector region coupled to ground potential, and an emitter region integral with said impedance means; and, d. a charge storage means coupled between the base and collector regions of said PNP transistor.
Claim 15
Dependent Claim
97 words
A noise suppression circuit having an input and an output, which comprises: a. a PNP transistor having a collector region, an emitter region coupled to the input of said circuit, and a base region coupled to an impedance means; b. an NPN transistor having a base region coupled to the collector region of said PNP transistor, a collector region coupled to a positive potential, and an emitter region coupled to said impedance means and to the output of said circuit; and, c. a charge storage means coupled between the base and collector regions of said NPN transistor.
Claim 16
Dependent Claim
97 words
A noise suppression circuit having an input and an output, which comprises: a. a PNP transistor having a collector region, an emitter region coupled to the input of said circuit, and a base region coupled to an impedance means; b. an NPN transistor having a base region coupled to the collector region of said PNP transistor, a collector region coupled to a positive potential, and an emitter region coupled to said impedance means and to the output of said circuit; and, c. a charge storage means coupled between the base and collector regions of said NPN transistor.
Claim 17
Dependent Claim
14 words
A circuit as defined in claim 12 wherein said impedance means comprises a diode.
References Cited (Backward Citations)
US3624288A
Cited
US3746885A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-08-04 | 1979-02-03 | 1979-08-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-08-04 | 1983-02-03 | 1983-08-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-08-04 | 1987-02-03 | 1987-08-05 | $7700.00 | Window Closed / Lapsed |