US3746885A
Expired / Lapsed
US
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Improved logic circuit using a current switch to compensate for signal deterioration
Assignee: Unisys Corp
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Filing: 1971-07-06
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Granted: 1973-07-17
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Expires: 1991-07-06
Abstract
Abstract An improved logic circuit comprising an input semiconductor, an output semiconductor and a current switch connected therebetween to compensate for signal deterioration in the logic circuit. The input semiconductor is biased to remain unsaturated in response to a binary signal swing at an input terminal. In an AND gate, the input semiconductor is a multi-emitter transistor; in an OR gate, the input semiconductor is a plurality of transistors.
Inventors
- 👤 Herbert Stopper
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 17:49
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/082; H03K19/086; H03K19/0863; H03K19/088
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
75 words
An improved logic circuit comprising: input semiconductive means having a base terminal, a collector terminal and an emitter terminal, output semiconductor means having a base terminal, a collector terminal and an emitter terminal, impedance means coupled between the base of said input semiconductor means and the base of said output semiconductive means, and alternatively conducting compensating means coupled to respective opposite ends of said impedance means for compensating for signal deterioration in said logic circuit.
Claim 2
Dependent Claim
75 words
An improved logic circuit comprising: input semiconductive means having a base terminal, a collector terminal and an emitter terminal, output semiconductor means having a base terminal, a collector terminal and an emitter terminal, impedance means coupled between the base of said input semiconductor means and the base of said output semiconductive means, and alternatively conducting compensating means coupled to respective opposite ends of said impedance means for compensating for signal deterioration in said logic circuit.
Claim 3
Dependent Claim
27 words
The improved logic circuit of claim 1 wherein said logic circuit performs the logical AND function and wherein said input semiconductive means includes a multiple emitter transistor.
Claim 4
Dependent Claim
25 words
The improved logic circuit according to claim 1 wherein the circuit performs logical OR functions and wherein said imput means includes a plurality of transistors.
Claim 5
Dependent Claim
17 words
The improVed logic circuit according to claim 1 wherein said compensating means includes a plurality of transistors.
Claim 6
Dependent Claim
25 words
The improved logic circuit according to claim 1 wherein said compensating means includes a plurality of transistors having one set of common electrodes coupled together.
Claim 7
Dependent Claim
15 words
The improved logic circuit according to claim 1 wherein said impedance means is a resistor.
Claim 8
Dependent Claim
50 words
The improved logic circuit according to claim 1 wherein said compensation means includes a first transistor for defining a first current path for increasing the output of said output semiconductive means and a second transistor for defining a second current path for decreasing the output of said output semiconductive means.
Claim 9
Dependent Claim
124 words
An improved logic circuit for providing an approximately unity transfer characteristic between the input and output signals thereof comprising: a multiple emitter input transistor including a base terminal, an output transistor including a base terminal, impedance means coupling the base terminals of said input and output transistors, means defining a first current path for increasing the signal of the output transistor to a given level when said output signal is intended to identify a first logic state, and means defining a second current path for decreasing the signal of said output transistor to another level when said output signal is intended to identify a different logic state, said signal increasing and decreasing means being respectively coupled to the opposite ends of said impedance means.
Claim 10
Dependent Claim
124 words
An improved logic circuit for providing an approximately unity transfer characteristic between the input and output signals thereof comprising: a multiple emitter input transistor including a base terminal, an output transistor including a base terminal, impedance means coupling the base terminals of said input and output transistors, means defining a first current path for increasing the signal of the output transistor to a given level when said output signal is intended to identify a first logic state, and means defining a second current path for decreasing the signal of said output transistor to another level when said output signal is intended to identify a different logic state, said signal increasing and decreasing means being respectively coupled to the opposite ends of said impedance means.
References Cited (Backward Citations)
US3015733A
Cited
US3283170A
Cited
US3283180A
Cited
DE1253759B
Cited
US3416003A
Cited
US3430071A
Cited
FR1460010A
Cited
US3515899A
Cited
US3479524A
Cited
US3579272A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-07-16 | 1977-01-15 | 1977-07-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-07-16 | 1981-01-15 | 1981-07-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-07-16 | 1985-01-15 | 1985-07-17 | $7700.00 | Window Closed / Lapsed |