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US3897643A Expired / Lapsed US ⏱️ 0.0 years remaining

Integrated heater element array and drive matrix

Assignee: Texas Instruments Inc
•
Filing: 1971-10-28
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Granted: 1975-08-05
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Expires: 1991-10-28
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Abstract

Abstract Thermal display including an air isolated integrated semiconductor circuit forming an array of semiconductor heater elements having different heights, widths and shapes joined by a metallic connecting pattern which extends out over the heating elements to interconnect selected ones of them and a PN junction isolated integrated semiconductor drive matrix for the heating element array positioned in the same plane as the heating element array. The PN junction isolated integrated semiconductor drive matrix and the semiconductor heating element array are concurrently formed in the same semiconductor substrate and the heating element array is air isolated to provide a high degree of electrical and thermal isolation for the heating element array while both are located in the same plane on a larger support. The thermally sensitive material on which a dynamic display is formed or on which a permanent display is printed is in direct contact with the monocrystalline semiconductor material of the heating element array and can be passed over the heating element array and the drive matrix.

Inventors

  • 👤 Jr Marvin L Morris
  • 👤 Jr Hermon L Pope
  • 👤 Edward M Ruggiero

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-05 04:26
CPC Classifications
H; H05; H05B; H05B3/00; H05B3/20; H05B3/22; H05B3/26; B; B41; B41J; B41J2/00; B41J2/315; B41J2/32; B41J2/335; B41J2/34; B41J2/485; B41J2/50; H05B1/00; H05B1/02; H05B1/0227; H10; H10W; H10W20/00; H10W20/20; H05B2203/00; H05B2203/013; H05B2203/035; H10W72/00; H10W72/50; H10W72/541; H10W72/5449

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 283 words
A thermal display comprising: a. an insulating substrate; b. a semiconductor wafer having one face mounted on said insulating substrate by an insulating adhesive, said semiconductor wafer comprising a plurality of physically separated wafer parts forming an array, said wafer parts respectively comprising heat dissipative elements of different heights and widths positioned at said one face to provide overlapping boundaries between adjaCent elements in diagonal and curved line directions, said heat dissipative elements being electrically and thermally isolated from each other, said wafer parts being formed in a first area of said semiconductor wafer; c. means coupled to said heat dissipative elements for selectively energizing said elements; d. a plurality of circuit elements formed on said one face in a second spaced area of said semiconductor wafer, the number of said plurality of circuit elements being at least as large as the number of said plurality of heat dissipative elements, said second area having P-N junctions which electrically isolate said plurality of circuit elements from one another through the semiconductor material, said second area of said semiconductor wafer being integral throughout; e. conductive means located between said one face and said insulating substrate electrically interconnecting said heat dissipative elements and said plurality of circuit elements, said second area being larger than said first area and the number of said plurality of circuit elements being larger than the number of said plurality of heat dissipative elements, said conductive means comprising diffused conductive tunnels in said one face of said semiconductor wafer between said first and second areas of said semiconductor wafer; and f. thermally sensitive means disposed near the opposite face of said semiconductor wafer and thermally coupled to said array of wafer parts.
Claim 2
Dependent Claim 283 words
A thermal display comprising: a. an insulating substrate; b. a semiconductor wafer having one face mounted on said insulating substrate by an insulating adhesive, said semiconductor wafer comprising a plurality of physically separated wafer parts forming an array, said wafer parts respectively comprising heat dissipative elements of different heights and widths positioned at said one face to provide overlapping boundaries between adjaCent elements in diagonal and curved line directions, said heat dissipative elements being electrically and thermally isolated from each other, said wafer parts being formed in a first area of said semiconductor wafer; c. means coupled to said heat dissipative elements for selectively energizing said elements; d. a plurality of circuit elements formed on said one face in a second spaced area of said semiconductor wafer, the number of said plurality of circuit elements being at least as large as the number of said plurality of heat dissipative elements, said second area having P-N junctions which electrically isolate said plurality of circuit elements from one another through the semiconductor material, said second area of said semiconductor wafer being integral throughout; e. conductive means located between said one face and said insulating substrate electrically interconnecting said heat dissipative elements and said plurality of circuit elements, said second area being larger than said first area and the number of said plurality of circuit elements being larger than the number of said plurality of heat dissipative elements, said conductive means comprising diffused conductive tunnels in said one face of said semiconductor wafer between said first and second areas of said semiconductor wafer; and f. thermally sensitive means disposed near the opposite face of said semiconductor wafer and thermally coupled to said array of wafer parts.
Claim 3
Dependent Claim 20 words
The thermal display claimed in claim 1 wherein the corners of selected ones of said heat dissipative elements are blunted.
Claim 4
Dependent Claim 17 words
The thermal display claimed in claim 1 wherein selected ones of said heat dissipative elements are curved.

References Cited (Backward Citations)

US2583184A Cited
US3096594A Cited
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US3495070A Cited
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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1978-08-04 1979-02-03 1979-08-05 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1982-08-04 1983-02-03 1983-08-05 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1986-08-04 1987-02-03 1987-08-05 $7700.00 Window Closed / Lapsed

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