Method of forming silicon gate device structures with two or more gate levels

Claim 1

A METHOD OF PRODUCING A SEMICONDUCTOR DEVICE ON A SUBSTRATE, THE DEVICE HAVING AT LEAST TWO LAYERS OF POLYCRYSTALLINE SILICON AT DIFFERENT LEVELS RELATIVE TO THE SUBSTRATE, AN EDGE OF ONE LAYER AT LEAST SUBSTANTIALLY COINCIDENT WITH AN EDGE OF ANOTHER LAYER COMPRISING: A. FORMING A LAYER OF FIELD OXIDE ON A SURFACE OF A SINGLE CRYSTAL SUBSTRATE AND DEFINING A WINDOW OF EXPOSED SUBSTRATE AT A PREDETERMINED POSITION FOR FORMING AT LEAST ONE DEVICE, B. GROWING A LAYER OF GATE OXIDE ON THE EXPOSED SURFACE OF SAID SUBSTRATE IN SAID WINDOW, C. DEPOSITING A FIRST LAYER OF POLYCRYSTALLINE SILICON ON SAID LAYER OF GATE OXIDE AND THE EXPOSED SURFACE OF SAID FIELD OXIDE, D. FORMING A LAYER TO FORM A FIRST MASKING LAYER ON SAID FIRST LAYER OF POLYCRYSTALLINE SILICON, E. ETCHING SAID FIRST MASKING LAYER AND SAID FIRST POLYCRYSTALLINE SILICON LAYER TO FORM SEPARATED PORTIONS OF SAID FIRST POLYCRYSTALLINE SILICON LAYER AT PREDETERMINED POSITIONS, F. THERMALLY OXIDIZING THE STRUCTURE TO FORM AN OXIDE LAYER ENCOMPASSING SAID PORTION OF SAID FIRST POLYCRYSTALLINE SILICON LAYER, SAID OXIDE LAYER INCORPORATING UNMASKED REGIONS OF SAID GATE OXIDE LAYER AND EXTENDING INTO SAID SUBSTRATE AT UNMASKED REGIONS OF SAID SUBSTRATE, G. DEPOSITING A SECOND LAYER OF POLYCRYSTALLINE SILICON ON SAID OXIDE LAYER FORMED IN (F) AND ON THE EXPOSED SURFACE OF SAID FIELD OXIDE, H. FORMING A FURTHER LAYER TO FORM A SECOND MASKING LAYER, ON SAID SECOND LAYER OF POLYCRYSTALLINE SILICON, I. ETCHING SEQUENTIALLY SAID SECOND MASKING LAYER AND SAID SECOND POLYCRYSTALLINE SILICON LAYER AND SAID OXIDE LAYER TO FORM AND UNCOVER AT LEAST ONE PORTION OF SAID SECOND POLYCRYSTALLINE LAYER IN A PREDETERMINED POSITIONED RELATIONSHIP WITH SAID SEPARATED PORTIONS OF SAID FIRST POLYCRYSTALLINE SILICON LAYER FOR FORMATION OF SAID DEVICE, TO UNCOVER AT LEAST A MAJOR PART OF SAID SEPARATE PORTION OF SAID FIRST LAYER OF POLYCRYSTALLINE SILICON, AND TO UNCOVER SAID SUBSTRATE AT POSITIONS NOT MASKED BY SAID FIELD OXIDE LAYER AND POLYCRYSTALLINE SILICON LAYERS, J. DOPING UNMASKED PORTIONS OF SAID POLYCRYSTALLINE SILICON LAYERS AND SIMULTANEOUSLY DOPING SAID SUBSTRATE AT SAID UNCOVERED AREAS TO FORM SOURCE AND DRAIN AREAS ASSOCIATED WITH SAID DEVICE AS REQUIRED, K. FORMING A DIELECTRIC LAYER ON EACH OF SAID DEVICES, AND I. FORMING ELECTRICAL CONTACT AREAS.

Claim 2

A METHOD OF PRODUCING A SEMICONDUCTOR DEVICE ON A SUBSTRATE, THE DEVICE HAVING AT LEAST TWO LAYERS OF POLYCRYSTALLINE SILICON AT DIFFERENT LEVELS RELATIVE TO THE SUBSTRATE, AN EDGE OF ONE LAYER AT LEAST SUBSTANTIALLY COINCIDENT WITH AN EDGE OF ANOTHER LAYER COMPRISING: A. FORMING A LAYER OF FIELD OXIDE ON A SURFACE OF A SINGLE CRYSTAL SUBSTRATE AND DEFINING A WINDOW OF EXPOSED SUBSTRATE AT A PREDETERMINED POSITION FOR FORMING AT LEAST ONE DEVICE, B. GROWING A LAYER OF GATE OXIDE ON THE EXPOSED SURFACE OF SAID SUBSTRATE IN SAID WINDOW, C. DEPOSITING A FIRST LAYER OF POLYCRYSTALLINE SILICON ON SAID LAYER OF GATE OXIDE AND THE EXPOSED SURFACE OF SAID FIELD OXIDE, D. FORMING A LAYER TO FORM A FIRST MASKING LAYER ON SAID FIRST LAYER OF POLYCRYSTALLINE SILICON, E. ETCHING SAID FIRST MASKING LAYER AND SAID FIRST POLYCRYSTALLINE SILICON LAYER TO FORM SEPARATED PORTIONS OF SAID FIRST POLYCRYSTALLINE SILICON LAYER AT PREDETERMINED POSITIONS, F. THERMALLY OXIDIZING THE STRUCTURE TO FORM AN OXIDE LAYER ENCOMPASSING SAID PORTION OF SAID FIRST POLYCRYSTALLINE SILICON LAYER, SAID OXIDE LAYER INCORPORATING UNMASKED REGIONS OF SAID GATE OXIDE LAYER AND EXTENDING INTO SAID SUBSTRATE AT UNMASKED REGIONS OF SAID SUBSTRATE, G. DEPOSITING A SECOND LAYER OF POLYCRYSTALLINE SILICON ON SAID OXIDE LAYER FORMED IN (F) AND ON THE EXPOSED SURFACE OF SAID FIELD OXIDE, H. FORMING A FURTHER LAYER TO FORM A SECOND MASKING LAYER, ON SAID SECOND LAYER OF POLYCRYSTALLINE SILICON, I. ETCHING SEQUENTIALLY SAID SECOND MASKING LAYER AND SAID SECOND POLYCRYSTALLINE SILICON LAYER AND SAID OXIDE LAYER TO FORM AND UNCOVER AT LEAST ONE PORTION OF SAID SECOND POLYCRYSTALLINE LAYER IN A PREDETERMINED POSITIONED RELATIONSHIP WITH SAID SEPARATED PORTIONS OF SAID FIRST POLYCRYSTALLINE SILICON LAYER FOR FORMATION OF SAID DEVICE, TO UNCOVER AT LEAST A MAJOR PART OF SAID SEPARATE PORTION OF SAID FIRST LAYER OF POLYCRYSTALLINE SILICON, AND TO UNCOVER SAID SUBSTRATE AT POSITIONS NOT MASKED BY SAID FIELD OXIDE LAYER AND POLYCRYSTALLINE SILICON LAYERS, J. DOPING UNMASKED PORTIONS OF SAID POLYCRYSTALLINE SILICON LAYERS AND SIMULTANEOUSLY DOPING SAID SUBSTRATE AT SAID UNCOVERED AREAS TO FORM SOURCE AND DRAIN AREAS ASSOCIATED WITH SAID DEVICE AS REQUIRED, K. FORMING A DIELECTRIC LAYER ON EACH OF SAID DEVICES, AND I. FORMING ELECTRICAL CONTACT AREAS.

Claim 7

A method of producing a multiplicity of silicon gate devices on a substrate, said devices comprising at least one device at one region and having two layers of polycrystalline silicon at different levels relative to said substrate and at least one device at a further region and having a layer of polycrystalline silicon at a level corresponding to one of said two layers of polycrystalline silicon, comprising: a. forming a layer of field oxide on a surface of a single crystal substrate and defining windows of exposed substrate in said layer of said oxide at positions for forming devices at said regions; b. growing a layer of gate oxide on the exposed surface of said substrate in said windows; c. depositing a first layer of polycrystalline silicon on said layer of gate oxide and the exposed surface of said field oxide; d. forming a layer to form a first masking layer on said first layer of polycrystalline silicon; e. etching said first masking layer and said first polycrystalline silicon layer to form separated portions of said first polycrystalline silicon layer for said device at said one region, and for forming anny desired portions of said first polycrystalline silicon layer for said device at said further region; f. thermally oxidizing the structure to form an oxide layer encompassing said portions of said first polycrystalline silicon layer, said oxide layer incorporating unmasked regions of said gate oxide layer and extending into said substrate at unmasked regions of said substrate; g. depositing a second layer of polycrystalline silicon on said oxide layer formed in (f) and on the exposed surface of said field oxide; h. forming a further layer to form a second masking layer, on said second layer of polycrystalline silicon; i. etching sequentially said second masking layer, said second polycrystalline silicon layer and said oxide layer to form and uncover at least one portion of said second polycrystalline silicon layer in a predetermined relationship with said separated portions of said first polycrystalline silicon layer for formation of said device at said one region and to form any desired portion of said second polycrystalline silicon layer for formation of said device at said further region, to uncover at least a major part of said separate portion of said first layer of polycrystalline silicon; and to form defined uncovered areas of substrate; j. doping unmasked portions of said polycrystalline silicon layers and simultaneously doping said substrate at said uncovered aReas to form source and drain areas associated with a device as required; k. forming a dielectric layer on each of said devices; and l. forming electrical contact areas.

Claim 8

A method of producing a multiplicity of silicon gate devices on a substrate, said devices comprising at least one device at one region and having two layers of polycrystalline silicon at different levels relative to said substrate and at least one device at a further region and having a layer of polycrystalline silicon at a level corresponding to one of said two layers of polycrystalline silicon, comprising: a. forming a layer of field oxide on a surface of a single crystal substrate and defining windows of exposed substrate in said layer of said oxide at positions for forming devices at said regions; b. growing a layer of gate oxide on the exposed surface of said substrate in said windows; c. depositing a first layer of polycrystalline silicon on said layer of gate oxide and the exposed surface of said field oxide; d. forming a layer to form a first masking layer on said first layer of polycrystalline silicon; e. etching said first masking layer and said first polycrystalline silicon layer to form separated portions of said first polycrystalline silicon layer for said device at said one region, and for forming anny desired portions of said first polycrystalline silicon layer for said device at said further region; f. thermally oxidizing the structure to form an oxide layer encompassing said portions of said first polycrystalline silicon layer, said oxide layer incorporating unmasked regions of said gate oxide layer and extending into said substrate at unmasked regions of said substrate; g. depositing a second layer of polycrystalline silicon on said oxide layer formed in (f) and on the exposed surface of said field oxide; h. forming a further layer to form a second masking layer, on said second layer of polycrystalline silicon; i. etching sequentially said second masking layer, said second polycrystalline silicon layer and said oxide layer to form and uncover at least one portion of said second polycrystalline silicon layer in a predetermined relationship with said separated portions of said first polycrystalline silicon layer for formation of said device at said one region and to form any desired portion of said second polycrystalline silicon layer for formation of said device at said further region, to uncover at least a major part of said separate portion of said first layer of polycrystalline silicon; and to form defined uncovered areas of substrate; j. doping unmasked portions of said polycrystalline silicon layers and simultaneously doping said substrate at said uncovered aReas to form source and drain areas associated with a device as required; k. forming a dielectric layer on each of said devices; and l. forming electrical contact areas.

Claim 18

A method of producing a multiplicity of silicon gate semiconductor devices on a substrate, said devices comprising a device of the charge coupled type having at least two layers of polycrystalline silicon at different levels relative to the substrate, and at least one other form of silicon gate device having a layer of polycrystalline silicon at a level corresponding with the lower of said levels of said charge coupled type, comprising: a. forming a layer of field oxide on a surface of a substrate and defining windows of exposed substrate at spaced regions, one region for said charged coupled type and a further region for each other device; b. growing a layer of gate oxide on the exposed surface of said substrate at said regions; c. depositing a first layer of polycrystalline silicon on said layer of gate oxide and the exposed surface of said field oxide; d. forming a layer to form a first masking layer on said first layer of polycrystalline silicon; e. etching said first masking layer and said first polycrystalline silicon layer to form separated portions of said first polycrystalline silicon layer at predetermined positions at said one region, and a portion of said first polycrystalline silicon layer at a further region; f. thermally oxidizing the structure to form an oxide layer encompassing said portions of said first polycrystalline silicon layer, said oXide layer incorporating unmasked regions of said gate oxide layer and extending into said substrate at unmasked regions of said substrate; g. depositing a second layer of polycrystalline silicon on said oxide layer formed in (f) and on the exposed surface of said field oxide; h. forming a further layer to form a second masking layer, on said second layer of polycrystalline silicon; i. etching sequentially said second masking layer, said second polycrystalline silicon layer and said oxide layer to form at least one portion of said second polycrystalline layer at said one region, said one portion positioned over a gap between said separated portions of said first polycrystalline silicon layer, the edges of said one portion at least coincident with the edges of said separated portions for formation of said device of charge coupled type; to uncover said portions of the polycrystalline silicon layers and to uncover said substrate at positions not masked by said field oxide and said portions of the polycrystalline silicon layers, j. doping unmasked portions of said polycrystalline silicon layers and simultaneously doping said substrate at said uncovered areas to form source and drain areas associated with said devices as required; k. forming a dielectric layer on each of said devices, and l. forming electrical contact areas.

Claim 19

A method of producing a multiplicity of silicon gate semiconductor devices on a substrate, said devices comprising a device of the charge coupled type having at least two layers of polycrystalline silicon at different levels relative to the substrate, and at least one other form of silicon gate device having a layer of polycrystalline silicon at a level corresponding with the lower of said levels of said charge coupled type, comprising: a. forming a layer of field oxide on a surface of a substrate and defining windows of exposed substrate at spaced regions, one region for said charged coupled type and a further region for each other device; b. growing a layer of gate oxide on the exposed surface of said substrate at said regions; c. depositing a first layer of polycrystalline silicon on said layer of gate oxide and the exposed surface of said field oxide; d. forming a layer to form a first masking layer on said first layer of polycrystalline silicon; e. etching said first masking layer and said first polycrystalline silicon layer to form separated portions of said first polycrystalline silicon layer at predetermined positions at said one region, and a portion of said first polycrystalline silicon layer at a further region; f. thermally oxidizing the structure to form an oxide layer encompassing said portions of said first polycrystalline silicon layer, said oXide layer incorporating unmasked regions of said gate oxide layer and extending into said substrate at unmasked regions of said substrate; g. depositing a second layer of polycrystalline silicon on said oxide layer formed in (f) and on the exposed surface of said field oxide; h. forming a further layer to form a second masking layer, on said second layer of polycrystalline silicon; i. etching sequentially said second masking layer, said second polycrystalline silicon layer and said oxide layer to form at least one portion of said second polycrystalline layer at said one region, said one portion positioned over a gap between said separated portions of said first polycrystalline silicon layer, the edges of said one portion at least coincident with the edges of said separated portions for formation of said device of charge coupled type; to uncover said portions of the polycrystalline silicon layers and to uncover said substrate at positions not masked by said field oxide and said portions of the polycrystalline silicon layers, j. doping unmasked portions of said polycrystalline silicon layers and simultaneously doping said substrate at said uncovered areas to form source and drain areas associated with said devices as required; k. forming a dielectric layer on each of said devices, and l. forming electrical contact areas.

Claim 20

A method of producing a multiplicity of silicon gate semiconductor devices on a substrate, said devices comprising a device of the charge coupled type having at least two layers of polycrystalline silicon at different levels relative to the substrate, and at least one other form of silicon gate device having a layer of polycrystalline silicon at a level corresponding with one of said levels above the lower level of said charge coupled type, comprising: a. forming a layer of field oxide on a surface of a substrate and defining windows of exposed substrate at spaced regions, one region for said charge coupled type and a further region for each other device; b. growing a layer of gate oxide on the exposed surface of said substrate at said regions; c. depositing a first layer of polycrystalline silicon on said layer of gate oxide and the exposed surface of said field oxide; d. forming a layer to form a first masking layer on said first layer of polycrystalline silicon; e. etching said first masking layer and said first polycrystalline silicon layer to form separated portions of said first polycrystalline silicon layer at predetermined positions at said one region; f. thermally oxidizing the structure to form an oxide layer encompassing said portion of said first polycrystalline silicon layer, said oxide layer incorporating unmasked regions of said gate oxide layer and extending into said substrate at unmasked regions of said substrate; g. depositing a second layer of polycrystalline silicon on said oxide layer formed in (f) and on the exposed surface of said field oxide; h. forming a further layer to form a second masking layer, on said second layer of polycrystalline silicon; i. etching said second masking layer, said second polycrystalline silicon layer and said oxide layer to form at least one portion of said second polycrystalline layer at said one region, said one portion positioned over a gap between said separated portions of said first polycrystalline silicon layer the edges of said one portion at least coincident with the edges of said separated portion for formation of said device of charge coupled type; to form a portion of said second polycrystalline silicon layer at a further region; to uncover said portions of the polycrystalline layers; and to uncover said substrate at positions not masked by said field oxide and said portions of the polycrystalline silicon layers; j. doping unmasked portions of said polycrystalline silicon layers and simultaneously doping said substrate at said uncovered areas to form source and drain areas associated with said device as reQuired; k. forming a dielectric layer on each of said devices, and l. forming electrical contact areas.

Claim 21

A method of producing a multiplicity of silicon gate semiconductor devices on a substrate, said devices comprising a device of the charge coupled type having at least two layers of polycrystalline silicon at different levels relative to the substrate, and at least one other form of silicon gate device having a layer of polycrystalline silicon at a level corresponding with one of said levels above the lower level of said charge coupled type, comprising: a. forming a layer of field oxide on a surface of a substrate and defining windows of exposed substrate at spaced regions, one region for said charge coupled type and a further region for each other device; b. growing a layer of gate oxide on the exposed surface of said substrate at said regions; c. depositing a first layer of polycrystalline silicon on said layer of gate oxide and the exposed surface of said field oxide; d. forming a layer to form a first masking layer on said first layer of polycrystalline silicon; e. etching said first masking layer and said first polycrystalline silicon layer to form separated portions of said first polycrystalline silicon layer at predetermined positions at said one region; f. thermally oxidizing the structure to form an oxide layer encompassing said portion of said first polycrystalline silicon layer, said oxide layer incorporating unmasked regions of said gate oxide layer and extending into said substrate at unmasked regions of said substrate; g. depositing a second layer of polycrystalline silicon on said oxide layer formed in (f) and on the exposed surface of said field oxide; h. forming a further layer to form a second masking layer, on said second layer of polycrystalline silicon; i. etching said second masking layer, said second polycrystalline silicon layer and said oxide layer to form at least one portion of said second polycrystalline layer at said one region, said one portion positioned over a gap between said separated portions of said first polycrystalline silicon layer the edges of said one portion at least coincident with the edges of said separated portion for formation of said device of charge coupled type; to form a portion of said second polycrystalline silicon layer at a further region; to uncover said portions of the polycrystalline layers; and to uncover said substrate at positions not masked by said field oxide and said portions of the polycrystalline silicon layers; j. doping unmasked portions of said polycrystalline silicon layers and simultaneously doping said substrate at said uncovered areas to form source and drain areas associated with said device as reQuired; k. forming a dielectric layer on each of said devices, and l. forming electrical contact areas.

Claim 22

A method of producing a multiplicity of silicon gate semiconductor devices on a substrate, said devices comprising a device of the charge coupled type having at least two layers of polycrystalline silicon at different levels relative to the substrate, and at least one other form of silicon gate device having a layer of polycrystalline silicon at a level corresponding with the lower of said levels of said charge coupled type comprising: a. forming a layer of field oxide on a surface of a substrate and defining windows of exposed substrate at spaced regions, one region for said charged coupled type and a further region for each other device; b. growing a layer of gate oxide on the exposed surface of said substrate at said regions; c. depositing a first layer of polycrystalline silicon on said layer of gate oxide and the exposed surface of said field oxide; d. forming a layer to form a first masking layer on said first layer of polycrystalline silicon; e. etching said first masking layer and said first polycrystalline silicon layer to form separated portions of said first polycrystalline silicon layer at predetermined positions at said one region, and a portion of said first polycrystalline silicon layer at a further region; f. thermally oxidizing the structure to form an oxide layer encompassing said portions of said first polycrystalline silicon layer, said oxide layer incorporating unmasked regions of said gate oxide layer and extending into said substrate at unmasked regions of said substrate; g. depositing a second layer of polycrystalline silicon on said oxide layer formed in (f) and on the exposed surface of said field oxide; h. forming a further layer to form a masking layer, on said second layer of polycrystalline silicon; i. etching said second masking layer, said second polycrystalline layer and said oxide layer to form at least one portion of said second polycrystalline layer at said one region, said one portion positioned over a gap between said separated portions of said first polycrystalline silicon layer, the edges of said one portion at least coincident with the edges of said separated portions, for formation of said device of charge coupled type; to form a portion of said second polycrystalline silicon layer at a further region, said portion of the second polycrystalline silicon layer at said further region overlapping said portion of said first polycrystalline silicon layer at said further region; to uncover said portions of the polycrystalline silicon layers; and to uncover said substrate at positions not masked by said field oxide and said portions of the polycrystalline silicon layers; j. doping unmasked portions of said polycrystalline silicon layers and simultaneously doping said substrate at said uncovered areas to form source and drain areas associated with said device as required; k. forming a dielectric layer on each of said devices, and l. forming electrical contact areas.

Claim 23

A method of producing a multiplicity of silicon gate semiconductor devices on a substrate, said devices comprising a device of the charge coupled type having at least two layers of polycrystalline silicon at different levels relative to the substrate, and at least one other form of silicon gate device having a layer of polycrystalline silicon at a level corresponding with the lower of said levels of said charge coupled type comprising: a. forming a layer of field oxide on a surface of a substrate and defining windows of exposed substrate at spaced regions, one region for said charged coupled type and a further region for each other device; b. growing a layer of gate oxide on the exposed surface of said substrate at said regions; c. depositing a first layer of polycrystalline silicon on said layer of gate oxide and the exposed surface of said field oxide; d. forming a layer to form a first masking layer on said first layer of polycrystalline silicon; e. etching said first masking layer and said first polycrystalline silicon layer to form separated portions of said first polycrystalline silicon layer at predetermined positions at said one region, and a portion of said first polycrystalline silicon layer at a further region; f. thermally oxidizing the structure to form an oxide layer encompassing said portions of said first polycrystalline silicon layer, said oxide layer incorporating unmasked regions of said gate oxide layer and extending into said substrate at unmasked regions of said substrate; g. depositing a second layer of polycrystalline silicon on said oxide layer formed in (f) and on the exposed surface of said field oxide; h. forming a further layer to form a masking layer, on said second layer of polycrystalline silicon; i. etching said second masking layer, said second polycrystalline layer and said oxide layer to form at least one portion of said second polycrystalline layer at said one region, said one portion positioned over a gap between said separated portions of said first polycrystalline silicon layer, the edges of said one portion at least coincident with the edges of said separated portions, for formation of said device of charge coupled type; to form a portion of said second polycrystalline silicon layer at a further region, said portion of the second polycrystalline silicon layer at said further region overlapping said portion of said first polycrystalline silicon layer at said further region; to uncover said portions of the polycrystalline silicon layers; and to uncover said substrate at positions not masked by said field oxide and said portions of the polycrystalline silicon layers; j. doping unmasked portions of said polycrystalline silicon layers and simultaneously doping said substrate at said uncovered areas to form source and drain areas associated with said device as required; k. forming a dielectric layer on each of said devices, and l. forming electrical contact areas.

Claim 24

A method of producing a multiplicity of silicon gate semiconductor devices on a substrate, said devices comprising a device of the charge coupled type having at least two layers of polycrystalline silicon at different levels relative to the substrate, and at least one other form of silicon gate device having a layer of polycrystalline silicon at a level corresponding with the lower of said levels of said charge coupled type, comprising: a. forming a layer of field oxide on a surface of a substrate and defining windows of exposed substrate at spaced regions, one region for said charged coupled type and a further region for each other device; b. growing a layer of gate oxide on the exposed surface of said substrate at said regions; c. depositing a first layer of polycrystalline silicon on said layer of gate oxide and the exposed surface of said field oxide; d. forming a laYer to form a first masking layer on said first layer of polycrystalline silicon; e. etching said first masking layer and said first polycrystalline silicon layer to form separated portions of said first polycrystalline silicon layer at predetermined positions at said one region, and a portion of said first polycrystalline silicon layer at a further region; f. thermally oxidizing the structure to form an oxide layer encompassing said portions of said first polycrystalline silicon layer, said oxide layer incorporating unmasked regions of said gate oxide layer and extending into said substrate at unmasked regions of said substrate; g. depositing a second layer of polycrystalline silicon on said oxide layer formed in (f) and on the exposed surface of said field oxide; h. forming a further layer to form a masking layer, on said second layer of polycrystalline silicon; i. etching said second masking layer, said second polycrystalline layer and said oxide layer to form at least one portion of said second polycrystalline layer at said one region, said one portion positioned over a gap between said separated portions of said first polycrystalline silicon layer, the edges of said one portion at least coincident with the edges of said separated portions, for formation of said device of charge coupled type; to form a portion of said second polycrystalline silicon layer at a further region, said portion of the second polycrystalline silicon layer at said further region overlying said portion of said first polycrystalline silicon layer at said further region; to uncover said portions of the polycrystalline silicon layers; and to uncover said substrate at positions not masked by said field oxide and said portions of the polycrystalline silicon layers; j. doping unmasked portions of said polycrystalline silicon layers and simultaneously doping said substrate at said uncovered areas to form source and drain areas associated with said device as required; k. forming a dielectric layer on each of said devices, and l. forming electrical contact areas.

Claim 25

A method of producing a multiplicity of silicon gate semiconductor devices on a substrate, said devices comprising a device of the charge coupled type having at least two layers of polycrystalline silicon at different levels relative to the substrate, and at least one other form of silicon gate device having a layer of polycrystalline silicon at a level corresponding with the lower of said levels of said charge coupled type, comprising: a. forming a layer of field oxide on a surface of a substrate and defining windows of exposed substrate at spaced regions, one region for said charged coupled type and a further region for each other device; b. growing a layer of gate oxide on the exposed surface of said substrate at said regions; c. depositing a first layer of polycrystalline silicon on said layer of gate oxide and the exposed surface of said field oxide; d. forming a laYer to form a first masking layer on said first layer of polycrystalline silicon; e. etching said first masking layer and said first polycrystalline silicon layer to form separated portions of said first polycrystalline silicon layer at predetermined positions at said one region, and a portion of said first polycrystalline silicon layer at a further region; f. thermally oxidizing the structure to form an oxide layer encompassing said portions of said first polycrystalline silicon layer, said oxide layer incorporating unmasked regions of said gate oxide layer and extending into said substrate at unmasked regions of said substrate; g. depositing a second layer of polycrystalline silicon on said oxide layer formed in (f) and on the exposed surface of said field oxide; h. forming a further layer to form a masking layer, on said second layer of polycrystalline silicon; i. etching said second masking layer, said second polycrystalline layer and said oxide layer to form at least one portion of said second polycrystalline layer at said one region, said one portion positioned over a gap between said separated portions of said first polycrystalline silicon layer, the edges of said one portion at least coincident with the edges of said separated portions, for formation of said device of charge coupled type; to form a portion of said second polycrystalline silicon layer at a further region, said portion of the second polycrystalline silicon layer at said further region overlying said portion of said first polycrystalline silicon layer at said further region; to uncover said portions of the polycrystalline silicon layers; and to uncover said substrate at positions not masked by said field oxide and said portions of the polycrystalline silicon layers; j. doping unmasked portions of said polycrystalline silicon layers and simultaneously doping said substrate at said uncovered areas to form source and drain areas associated with said device as required; k. forming a dielectric layer on each of said devices, and l. forming electrical contact areas.

Claim 26

A method of producing a multiplicity of silicon gate semiconductor devices on a substrate, said devices comprising a device of the charge couple type having at least two layers of polycrystalline silicon at different levels relative to the substrate, and at least one other form of silicon gate device having a layer of polycrystalline silicon at a level corresponding with the lower of said levels of said charge coupled type, comprising: a. forming a layer of field oxide on a surface of a substrate and defining windows of exposed substrate at spaced regions, one region for said charged coupled type and a further region for each other device; b. growing a layer of gate oxide on the exposed surface of said substrate at said regions; c. depositing a first layer of polycrystalline silicon on said layer of gate oxide and the exposed surface of said field oxide; d. forming a layer to form a first masking layer on said first layer of polycrystalline silicon; e. etching said first masking layer and said first polycrystalline silicon layer to form separated portions of said first polycrystalline silicon layer at predetermined positions at said one region, and spaced portions of said first polycrystalline silicon layer at a further region; f. thermally oxidizing the structure to form an oxide layer encompassing said portions of said first polycrystalline silicon layer, said oxide layer incorporating unmasked regions of said gate oxide layer and extending into said substrate at unmasked regions of said substrate; g. depositing a second layer of polycrystalline silicon on said oxide layer formed in (f) and on the exposed surface of said field oxide; h. forming a further layer to form a masking layer, on said second layer of polycrystalline silicon; i. etching said second masking layer, said second polycrystalline layer and said oxide layer to form at least onE portion of said second polycrystalline layer at said one region, said one portion positioned over a gap between said separated portions of said first polycrystalline silicon layer, the edges of said one portion at least coincident with the edges of said separated portions, for formation of said device of charge coupled type; to form a portion of said second polycrystalline silicon layer at said further region positioned over a gap between said separated portions of said first polycrystalline silicon layer at said further region, the edges of said portion of said second polycrystalline silicon layer at least coincident with the edges of said spaced portions of said first polycrystalline silicon layer at said further region; to uncover said portions of the polycrystalline silicon layers; and to uncover said substrate at positions not masked by said field oxide and said portions of the polycrystalline silicon layers; j. doping unmasked portions of said polycrystalline silicon layers and simultaneously doping said substrate at said uncovered areas to form source and drain areas associated with said device as required; k. forming a dielectric layer on each of said devices, and l. forming electrical contact areas.

Claim 27

A method of producing a multiplicity of silicon gate semiconductor devices on a substrate, said devices comprising a device of the charge couple type having at least two layers of polycrystalline silicon at different levels relative to the substrate, and at least one other form of silicon gate device having a layer of polycrystalline silicon at a level corresponding with the lower of said levels of said charge coupled type, comprising: a. forming a layer of field oxide on a surface of a substrate and defining windows of exposed substrate at spaced regions, one region for said charged coupled type and a further region for each other device; b. growing a layer of gate oxide on the exposed surface of said substrate at said regions; c. depositing a first layer of polycrystalline silicon on said layer of gate oxide and the exposed surface of said field oxide; d. forming a layer to form a first masking layer on said first layer of polycrystalline silicon; e. etching said first masking layer and said first polycrystalline silicon layer to form separated portions of said first polycrystalline silicon layer at predetermined positions at said one region, and spaced portions of said first polycrystalline silicon layer at a further region; f. thermally oxidizing the structure to form an oxide layer encompassing said portions of said first polycrystalline silicon layer, said oxide layer incorporating unmasked regions of said gate oxide layer and extending into said substrate at unmasked regions of said substrate; g. depositing a second layer of polycrystalline silicon on said oxide layer formed in (f) and on the exposed surface of said field oxide; h. forming a further layer to form a masking layer, on said second layer of polycrystalline silicon; i. etching said second masking layer, said second polycrystalline layer and said oxide layer to form at least onE portion of said second polycrystalline layer at said one region, said one portion positioned over a gap between said separated portions of said first polycrystalline silicon layer, the edges of said one portion at least coincident with the edges of said separated portions, for formation of said device of charge coupled type; to form a portion of said second polycrystalline silicon layer at said further region positioned over a gap between said separated portions of said first polycrystalline silicon layer at said further region, the edges of said portion of said second polycrystalline silicon layer at least coincident with the edges of said spaced portions of said first polycrystalline silicon layer at said further region; to uncover said portions of the polycrystalline silicon layers; and to uncover said substrate at positions not masked by said field oxide and said portions of the polycrystalline silicon layers; j. doping unmasked portions of said polycrystalline silicon layers and simultaneously doping said substrate at said uncovered areas to form source and drain areas associated with said device as required; k. forming a dielectric layer on each of said devices, and l. forming electrical contact areas.