Patent US3894890A successfully refreshed from Google Patents.
US3894890A
Expired / Lapsed
US
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Method for improving the radiation resistance of silicon transistors
Assignee: Siemens AG
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Filing: 1973-07-06
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Granted: 1975-07-15
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Expires: 1993-07-06
Abstract
Abstract A method for improving the radiation resistance of silicon transistors of the type having silicon oxide cover layer in which a transistor or a silicon wafer with several transistor structures therein is exposed to electron radiation with an energy below 150 keV for a dose of between 109 and 1010 rad at the boundary layer between the silicon and the silicon oxide cover layer while being at a temperature of between 200* and 300*C. After the irradiation the transistor or silicon wafer is annealed for at least 10 hours at a temperature of between 200* and 300*C while a voltage of at least 0.3 V is applied in the forward direction between the emitter and the base terminal of the transistor or the transistor structures.
Inventors
- 👤 Rudolf Bauerlein
- 👤 Dieter Uhl
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 10:49
CPC Classifications
H; H10; H10P; H10P95/00; Y; Y10; Y10S; Y10S257/00; Y10S257/906; Y10S438/00; Y10S438/909; Y10S438/953
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
104 words
A METHOD OF IMPROVING THE RADIATION RESISTANCE OF A SILICON TRANSISTOR HAVING A SILICON OXIDE COVER LAYER COMPRISING THE STEPS OF: A. SUBJECTING THE TRANSISTOR TO ELECTRON RADIATION WITH AN ENERGY BELOW 150 KEV FOR A DOSE BETWEEN 10**9 AND 10**10 RAD AT THE BOUNDARY LAYER BETWEEN THE SILICON AND SILICON OXIDE WHILE MAINTAINING THE TRANSISTOR AT A TEMPERATURE BETWEEN 200*C AND 300*C, AND B. AFTER IRRADIATION, ANNEALING THE TRANSISTOR FOR AT LEAST 10 HOURS AT A TEMPERATURE BETWEEN 200*C AND 300*C WHILE APPLYING AN ELECTRICAL VOLTAGE OF AT LEAST 0.3 V ACROSS THE EMITTER AND BASE OF THE TRANSISTOR IN A FORWARD DIRECTION.
Claim 2
Independent Claim
104 words
A METHOD OF IMPROVING THE RADIATION RESISTANCE OF A SILICON TRANSISTOR HAVING A SILICON OXIDE COVER LAYER COMPRISING THE STEPS OF: A. SUBJECTING THE TRANSISTOR TO ELECTRON RADIATION WITH AN ENERGY BELOW 150 KEV FOR A DOSE BETWEEN 10**9 AND 10**10 RAD AT THE BOUNDARY LAYER BETWEEN THE SILICON AND SILICON OXIDE WHILE MAINTAINING THE TRANSISTOR AT A TEMPERATURE BETWEEN 200*C AND 300*C, AND B. AFTER IRRADIATION, ANNEALING THE TRANSISTOR FOR AT LEAST 10 HOURS AT A TEMPERATURE BETWEEN 200*C AND 300*C WHILE APPLYING AN ELECTRICAL VOLTAGE OF AT LEAST 0.3 V ACROSS THE EMITTER AND BASE OF THE TRANSISTOR IN A FORWARD DIRECTION.
Claim 3
Dependent Claim
19 words
The method according to claim 1 wherein a plurality of transistors structures on a common wafer are simultaneously processed.
Claim 4
Dependent Claim
35 words
The method according to claim 1 and further including the step of applying an electrical voltage of at least 0.3 V across the collector and base of the transistor in the forward direction during annealing.
Claim 5
Dependent Claim
18 words
The method according to claim 1 wherein the step of annealing is continued for at least 40 hours.
Claim 6
Dependent Claim
21 words
The method according to claim 1 wherein the steps of irradiation and annealing are performed with the transistor in a vacuum.
Claim 7
Dependent Claim
30 words
The method according to claim 1 and further including the step of enclosing the transistor in an air-tight capsule after annealing, said capsule being filled with a dry protective gas.
Claim 8
Dependent Claim
21 words
The method according to claim 1 and further including the step of covering the transistor with a plastic coating after annealing.
Claim 9
Dependent Claim
33 words
The method according to claim 1 and further including the steps of coating the transistor crystal with a coat of one of lacquer and plastic and then placing said crystal in a capsule.
Claim 10
Dependent Claim
35 words
The method according to claim 1 and further including the step of encapsulating the transistor in an air-tight capsule between the steps of irradiating and annealing which capsule is filled with a dry protective gas.
Claim 11
Dependent Claim
24 words
The methoD according to claim 1 wherein the steps of a irradiation and annealing are performed with the transistor in a dry protective gas.
Claim 12
Dependent Claim
22 words
The method according to claim 1 and further including the step of enclosing the transistor in an evacuated airtight capsule after annealing.
Claim 13
Dependent Claim
26 words
A method according to claim 1 and further including the step of encapsulating the transistor in an evacuated air-tight capsule between steps of irradiating and annealing.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-07-14 | 1979-01-13 | 1979-07-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-07-14 | 1983-01-13 | 1983-07-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-07-14 | 1987-01-13 | 1987-07-15 | $7700.00 | Window Closed / Lapsed |