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US3891973A
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Multi-function digital counter/timer
Assignee: Northrop Grumman Space and Mission Systems Corp
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Filing: 1973-08-16
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Granted: 1975-06-24
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Expires: 1993-08-16
Abstract
Abstract A plurality of numerical words to be incremented or decremented is serially stored in a cyclic binary shift register comprising an accumulator section and a memory section. All digits in the series are repeatedly circulated through the accumulator section upon which logic means operates to cause each digit value instantaneously contained therein to be selectively left unchanged or changed unitarily in a particular arithmetic modulus, depending on the identity of the digit. A counter monitors the circulation of digits and identifies the instantaneous content of the accumulator to permit the logic means to select the proper operation and modulus. Input and output means are provided, and an external clock may be employed to determine when each digit value should be changed, inserted, or extracted.
Inventors
- 👤 Jerome Eugene Maxwell
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 10:00
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/46; G06F9/48; G06F9/4806; G06F9/4812; G06F9/4825; G04; G04F; G04F1/00; G04F1/005; G04F10/00; G04F10/04; G04G; G04G99/00; G04G99/006
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
372 words
A multi-function numerical processor comprising: a. electronic storage means to store a plurality of independent numerical words, each of said words being logically represented within said storage means as an ordered series of digits, each of said digits being in a selected arithmetic modulus and logically represented as an ordered series of binary bits, the totality of said words being logically represented within said storage means as an ordered cyclic series of binary bits, said storage means comprising an accumulator adapted to store one of said digits and a memory adapted to store all portions of said word series not stored in said accumulator; b. shifting means to serially cause each of the binary bits comprising each of the digits stored within said storage means to exit said memory and enter said accumulator; c. logic means to act on any specific digit instantaneously stored within said accumulator to perform thereon an arithmetic operation in the arithmetic modulus of said specific digit, said operation comprising changing the modular magnitude of said specific digit unitarily in a selected algebraic sign if and only if the elapsed time since the last change in said digit exceeds a selected period, said electronic logic means comprising: 1. first electronic means to generate an electrical output signal indicative of the condition wherein an entire digit is instantaneously stored within said accumulator; 2. second electronic means to generate an electrical output signal representative of the identity of the specific digit; 3. third electronic means, responsive to the output from said second electronic means, to generate and electrical output signal representative of said algebraic sign; 4. chronometer means to generate an output signal indicating elapsed time; and 5. fourth electronic means, responsive to the output signals from said first electronic means, said third electronic means and said chronometer means, to perform said operation; d. means to cause the binary bits comprising each digit stored within said accumulator to serially return, subsequent to the activity of said electronic logic means, to said memory into the assigned logical position of that particular digit within said word series; and e. output means operable on said storage means to extract the instantaneous values of all digits constituting any selected one of said numerical words.
Claim 2
Dependent Claim
372 words
A multi-function numerical processor comprising: a. electronic storage means to store a plurality of independent numerical words, each of said words being logically represented within said storage means as an ordered series of digits, each of said digits being in a selected arithmetic modulus and logically represented as an ordered series of binary bits, the totality of said words being logically represented within said storage means as an ordered cyclic series of binary bits, said storage means comprising an accumulator adapted to store one of said digits and a memory adapted to store all portions of said word series not stored in said accumulator; b. shifting means to serially cause each of the binary bits comprising each of the digits stored within said storage means to exit said memory and enter said accumulator; c. logic means to act on any specific digit instantaneously stored within said accumulator to perform thereon an arithmetic operation in the arithmetic modulus of said specific digit, said operation comprising changing the modular magnitude of said specific digit unitarily in a selected algebraic sign if and only if the elapsed time since the last change in said digit exceeds a selected period, said electronic logic means comprising: 1. first electronic means to generate an electrical output signal indicative of the condition wherein an entire digit is instantaneously stored within said accumulator; 2. second electronic means to generate an electrical output signal representative of the identity of the specific digit; 3. third electronic means, responsive to the output from said second electronic means, to generate and electrical output signal representative of said algebraic sign; 4. chronometer means to generate an output signal indicating elapsed time; and 5. fourth electronic means, responsive to the output signals from said first electronic means, said third electronic means and said chronometer means, to perform said operation; d. means to cause the binary bits comprising each digit stored within said accumulator to serially return, subsequent to the activity of said electronic logic means, to said memory into the assigned logical position of that particular digit within said word series; and e. output means operable on said storage means to extract the instantaneous values of all digits constituting any selected one of said numerical words.
Claim 3
Dependent Claim
17 words
second electronic means to generate an electrical output signal representative of the identity of the specific digit;
Claim 4
Dependent Claim
17 words
second electronic means to generate an electrical output signal representative of the identity of the specific digit;
Claim 5
Dependent Claim
40 words
The processor, as recited in claim 1, further including input means, operable on said storage means, to change the value of any selected digit stored therein, said input means adapted, when activated, to override the activity of said logic means.
Claim 6
Dependent Claim
18 words
The processor, as recited in claim 2, wherein said input means operates on the contents of said accumulator.
Claim 7
Dependent Claim
23 words
third electronic means, responsive to the output from said second electronic means, to generate and electrical output signal representative of said algebraic sign;
Claim 8
Dependent Claim
23 words
third electronic means, responsive to the output from said second electronic means, to generate and electrical output signal representative of said algebraic sign;
Claim 9
Dependent Claim
11 words
chronometer means to generate an output signal indicating elapsed time; and
Claim 10
Dependent Claim
11 words
chronometer means to generate an output signal indicating elapsed time; and
Claim 11
Dependent Claim
16 words
The processor, as recited in claim 1, wherein said storage means comprises a binary shift register.
Claim 12
Dependent Claim
26 words
The processor, as recited in claim 4, wherein the logical format of said shift register is BCD and each of said bit series comprises four bits.
Claim 13
Dependent Claim
92 words
fourth electronic means, responsive to the output signals from said first electronic means, said third electronic means and said chronometer means, to perform said operation; d. means to cause the binary bits comprising each digit stored within said accumulator to serially return, subsequent to the activity of said electronic logic means, to said memory into the assigned logical position of that particular digit within said word series; and e. output means operable on said storage means to extract the instantaneous values of all digits constituting any selected one of said numerical words.
Claim 14
Dependent Claim
92 words
fourth electronic means, responsive to the output signals from said first electronic means, said third electronic means and said chronometer means, to perform said operation; d. means to cause the binary bits comprising each digit stored within said accumulator to serially return, subsequent to the activity of said electronic logic means, to said memory into the assigned logical position of that particular digit within said word series; and e. output means operable on said storage means to extract the instantaneous values of all digits constituting any selected one of said numerical words.
Claim 15
Dependent Claim
65 words
The processor, as recited in claim 4, wherein said shifting means and said return means comprise a cyclic clock, each cycle of said clock comprising a fixed number of discrete phases, said memory and said accumulator operably connected with said clock in such manner that a selected pair of said phases causes a unitary logical position shift of all bit values throughout said shift register.
Claim 16
Dependent Claim
21 words
The processor, as recited in claim 1, wherein a response of said fourth electronic means comprises selection of said arithmetic modulus.
Claim 17
Dependent Claim
17 words
The processor, as recited in claim 1, wherein said second electronic means comprises a binary ripple counter.
Claim 18
Dependent Claim
31 words
The processor, as recited in claim 6, wherein said chronometer means, generates fixed-interval time pulses, and said fourth electronic means, in response to said pulses, determines if said period is exceeded.
Claim 19
Dependent Claim
19 words
The processor, as recited in claim 9, wherein the duration of said cycle is independent of said fixed interval.
Claim 20
Dependent Claim
29 words
The processor, as recited in claim 9, wherein said cycle duration is fixed and said time pulse interval exceeds said cycle duration by a factor of at least 100.
Claim 21
Dependent Claim
12 words
The processor, as recited in claim 11, wherein said factor is integral.
Claim 22
Dependent Claim
14 words
The processor, as recited in claim 6, wherein said chronometer means comprises said clock.
Claim 23
Dependent Claim
35 words
The processor, as recited in claim 4, wherein said output means comprises output register means, to extract, from said storage means, a single digit stored therein during a single operation of said output register means.
Claim 24
Dependent Claim
28 words
The processor, as recited in claim 14, wherein said output register means is operably connected with said accumulator, and said digit is a digit stored in said accumulator.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-06-23 | 1978-12-23 | 1979-06-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-06-23 | 1982-12-23 | 1983-06-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-06-23 | 1986-12-23 | 1987-06-24 | $7700.00 | Window Closed / Lapsed |