Method and apparatus for processing calls distributed randomly in time and requiring response delays of any duration, but specified for each call

Claim 2

A circuit for processing calls distributed randomly in time and generated by a plurality of devices, each call being accompanied by a delay data item which represents the response delay required by the calling device in terms of a multiplier to be assigned to a predetermined minimum time interval d, comprising: a sequential control unit for controlling the operation of said circuit in cycles and for providing a succession of control order signals during each cycle; a plurality of call receivers, one receiver for each device; a sequential selection circuit for sequentially selecting said call receivers in response to said control order signals; a plurality of alterable memories, one alterable memory for eaCh device, each of said memories comprising means for chaining into a circular waiting queue a memory assigned to calling devices; a calculating network responsive to said control order signals for generating a first representation of the number of said cycles of operation of said circuit, a second representation of the number of said calling devices for which memories are chained into said queue, and a sum representation of the quantities represented by said first and second representations; and a transfer network responsive to said control order signals and coupled sequentially to said memories, to the ones of said call receivers selected by said selection circuit, and to said calculating network, for transferring to one of said memories the delay item provided by a calling device and the current sum representation generated by said calculating network.

Claim 3

A circuit for processing calls distributed randomly in time and generated by a plurality of devices, each call being accompanied by a delay data item which represents the response delay required by the calling device in terms of a multiplier to be assigned to a predetermined minimum time interval d, comprising: a sequential control unit for controlling the operation of said circuit in cycles and for providing a succession of control order signals during each cycle; a plurality of call receivers, one receiver for each device; a sequential selection circuit for sequentially selecting said call receivers in response to said control order signals; a plurality of alterable memories, one alterable memory for eaCh device, each of said memories comprising means for chaining into a circular waiting queue a memory assigned to calling devices; a calculating network responsive to said control order signals for generating a first representation of the number of said cycles of operation of said circuit, a second representation of the number of said calling devices for which memories are chained into said queue, and a sum representation of the quantities represented by said first and second representations; and a transfer network responsive to said control order signals and coupled sequentially to said memories, to the ones of said call receivers selected by said selection circuit, and to said calculating network, for transferring to one of said memories the delay item provided by a calling device and the current sum representation generated by said calculating network.

Claim 4

A circuit for processing calls distributed randomly in time and generated by a plurality of devices, each call being accompanied by a delay data item which represents the response delay required by the calling device in terms of a multiplier to be assigned to a predetermined minimum time interval d, comprising: a sequential control unit for controlling the operation of said circuit in cycles and for providing a succession of control order signals during each cycle; a plurality of call receivers, one receiver for each device; a sequential selection circuit for sequentially selecting said call receivers in response to said control order signals; a plurality of alterable memories, one alterable memory for eaCh device, each of said memories comprising means for chaining into a circular waiting queue a memory assigned to calling devices; a calculating network responsive to said control order signals for generating a first representation of the number of said cycles of operation of said circuit, a second representation of the number of said calling devices for which memories are chained into said queue, and a sum representation of the quantities represented by said first and second representations; and a transfer network responsive to said control order signals and coupled sequentially to said memories, to the ones of said call receivers selected by said selection circuit, and to said calculating network, for transferring to one of said memories the delay item provided by a calling device and the current sum representation generated by said calculating network.

Claim 5

The circuit of claim 1 wherein said sequential control unit comprises: a control memory for generating said control order signals in particular sequence, such signals representing orders for comparison which upon execution cause the modification of said sequence according to the results of the comparison effected, and; a pulse generator for triggering cycles of said control memory.

Claim 6

The circuit of claim 2 wherein said calculating network comprises an adder, a register having contents representing a fixed interval, a cycle counter, and an incrementer-decrementer, said incrementer-decrementer being responsive to certain of said control order signals for providing said second representation which evolves as a function of the number of said cycles and as a function of the number of calls chained in said circular waiting queue, wherein said adder delivers said sum representation which is a function of the sum of said register contents, said cycle counter and said second representation.

Claim 7

The circuit of claim 3, wherein said sequential selection circuit, while sequentially selecting said receivers, detects calls generated by the respective devices and enables the transfer of the identities of the calling devices and the corresponding delay data items.

Claim 8

The circuit of claim 4 wherein each of said call receivers comprises: an identity register for holding the identity of the device to which said call receiver is assigned; a response delay register for holding the delay data item accompanying a call generated by the corresponding device; and a call transfer device.

Claim 9

The circuit of claim 5 further comprising a memory selection circuit, said selection circuit comprising a selector register having input leads selectively coupled to output leads of said identity registers of said call receivers in response to said control order signals.

Claim 10

The circuit of claim 6 further comprising a plurality of comparators, wherein each of said alterable memories comprises: a test register; a delay decrementer register; said delay decrementer register being coupled through said transfer network to selected ones of said memories, the input lead of said test register being connected to said adder for receiving said sum representation, the output lead of said test register being connected to a first input lead of a first comparator, a second output lead of said first comparator being connected to said cycle counter, the input leads of said delay decrementer register being selectively connected to the response delay registers of said call receivers, the output lead of said delay decrementer register being connected to one input lead of a second comparator, a second input lead of such comparator continuously receiving a signal representing the number value 0.

Claim 11

The circuit of claim 7 wherein each one of said means for chaining of said memories comprises: a ''''preceding'''' identity register for identifying the device whose corresponding memory in said queue was chained into said queue immediately preceding the time of the chaining of the memory having said onE means for chaining; a ''''following'''' identity register for identifying the device whose corresponding memory in said queue was chained into said queue immediately following the time of the chaining of the memory having said one means for chaining.

Claim 12

The circuit of claim 8 further comprising a pointer register whose contents identify the device for which the sum representation stored in the test register of the corresponding memory is the closest to the time representation furnished by said cycle counter, said pointer register being selectively coupled to the output leads of said ''''following'''' identity registers by said transfer network under control of a control order signal, wherein the input leads of said ''''preceding'''' and ''''following'''' identity registers of one of said memories are selectively coupled, through said transfer network, under control order signal and said pointer register contents, to the respective output leads of said ''''preceding'''' identity registers and ''''following'''' identity registers of said memories, when the output lead of said second comparator denotes that the contents of said delay decrementer register of the memory corresponding to the device whose identity is held in said pointer register represents the number 0.

Claim 13

The circuit of claim 9 wherein said incrementer-decrementer of said calculating network is coupled to an incrementing-decrementing circuit which provides for: incrementing the contents of said incrementer-decrementer each time said sequential control unit transfers the representation of said adder to the test register of one of said memories; decrementing the contents of said incrementer-decrementer each time that said sequential control unit causes the progression of said cycle counter of said calculating network.

Claim 14

In a data processing system in which each of a plurality of devices makes calls requiring processing, and wherein in making such calls such device supplies a delay data item representing the delay after which the coresponding call is to be processed, the combination comprising: a plurality of memory elements, said elements being organized into a closed chain wherein each of said elements stores a representation of the preceding and following element in said chain, each of said elements further storing one of said delay data items and a test time item, said test time item representing the time when the corresponding delay data item should be tested to determine whether the respective call should be processed; a pointer register for holding a pointer representing one of the elements in said chain; a generator of a current time item representing the current time; a first comparator responsive to an input control signal and said pointer for comparing the test time item in the pointee element with said current time item and for delivering a first result signal denoting equality and a second result signal denoting inequality; means enabled after delivery of the first result signal of said first comparator for changing the value of the delay data item in said pointee element; a second comparator enabled after delivery of the first result signal of said first comparator and responsive to said pointer for comparing the delay data item in the pointee element with a predetermined number and for delivering a first result signal denoting equality and a second result signal denoting inequality; means responsive to the delivery of the first result signal of said second comparator for initiating processing of the call corresponding to the pointer, for removing the pointee element from said chain, and for changing the value of said pointer to represent the following element in said chain; and means responsive to the delivery of the second result signal of said second comparator for storing a new test time item in the pointee element.

Claim 15

In a data processing system in which each of a plurality of devices makes calls requiring processing, and wherein in making such calls such device supplies a delay data item representing the delay after which the coresponding call is to be processed, the combination comprising: a plurality of memory elements, said elements being organized into a closed chain wherein each of said elements stores a representation of the preceding and following element in said chain, each of said elements further storing one of said delay data items and a test time item, said test time item representing the time when the corresponding delay data item should be tested to determine whether the respective call should be processed; a pointer register for holding a pointer representing one of the elements in said chain; a generator of a current time item representing the current time; a first comparator responsive to an input control signal and said pointer for comparing the test time item in the pointee element with said current time item and for delivering a first result signal denoting equality and a second result signal denoting inequality; means enabled after delivery of the first result signal of said first comparator for changing the value of the delay data item in said pointee element; a second comparator enabled after delivery of the first result signal of said first comparator and responsive to said pointer for comparing the delay data item in the pointee element with a predetermined number and for delivering a first result signal denoting equality and a second result signal denoting inequality; means responsive to the delivery of the first result signal of said second comparator for initiating processing of the call corresponding to the pointer, for removing the pointee element from said chain, and for changing the value of said pointer to represent the following element in said chain; and means responsive to the delivery of the second result signal of said second comparator for storing a new test time item in the pointee element.

Claim 16

The combination of claim 11 further comprising: means responsive to a call By a device for temporarily storing the corresponding delay data item; means responsive to a call by a device and to said current time item for generating a test time item, said test time item representing an interval following the current time represented by said current time item after which said delay data item should be tested; and means following generation of said test time item for entering said test time item and corresponding delay data item in a separate memory element and responsive to said pointer for inserting said separate memory element into said chain in a position immediately preceding the pointee element.

Claim 17

The combination of claim 12 further comprising: a generator of regularly recurring stimuli, said stimuli being temporally spaced apart by a cyclic interval; and means for applying said stimuli to said first comparator as said input control signal thereto.

Claim 18

The combination of claim 13 wherein the interval represented by each of said test time items is at least a predetermined minimum number of said cyclic intervals and each of said delay data items represents an integral number of said minima.